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PMOS based 1-Bit Full Adder Cell
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 42 - Number 15 |
| Year of Publication: 2012 |
| Authors: Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh |
10.5120/5767-7984
|
Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh . PMOS based 1-Bit Full Adder Cell. International Journal of Computer Applications. 42, 15 ( March 2012), 8-18. DOI=10.5120/5767-7984
Abstract
This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity. It also shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations. Therefore, the proposed design outperforms the existing adder and proves to be an optimal option for low power and energy efficient applications. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13. 0.
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