The week's pick
Random Articles
Reseach Article
PMOS based 1-Bit Full Adder Cell
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 42 - Number 15 |
| Year of Publication: 2012 |
| Authors: Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh |
10.5120/5767-7984
|
Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh . PMOS based 1-Bit Full Adder Cell. International Journal of Computer Applications. 42, 15 ( March 2012), 8-18. DOI=10.5120/5767-7984
Abstract
This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity. It also shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations. Therefore, the proposed design outperforms the existing adder and proves to be an optimal option for low power and energy efficient applications. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13. 0.
References
- N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: Addison-Wesley, 1993.
- S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, 3rd ed.
- S. R. Chowdhury, A. Banerjee, A. Roy, H. Saha, " A high speed 8-transistor full adder design using novel 3 transistor XOR gates," International Journal of Electronics, Circuits and Systems, vol. 2, No. 4, pp. 217-223, 2008.
- T. Sharma, K. G. Sharma, Prof. B. P. Singh, Neha Arora, "A Novel CMOS 1-bit 8T Full Adder Cell," in World Scientific and Engineering Academy and Society (WSEAS) Transactions on Systems, vol. 9, No. 3, pp. 317-326, March 2010.
- D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, Y. Yang, "Novel Low Power Full Adder Cells in 180nm CMOS Technology," in Prod. IEEE ICIEA, pp. 430-433, 2009.
- S. Veeramachaneni, M. B. Srinivas, "New Improved 1-Bit Full Adder Cells," CCECE/ CCGEI, Niagara Falls. Canada, pp. 735-738, May 5-7 2008.
- T. Sharma, K. G. Sharma and Prof. B. P. Singh, "Energy Efficient 1-bit Full Adder Cell with 45% Reduced Threshold Loss," International Journal of Recent Trends in Engineering, vol 3, pp. 106-110, 2010.
- Austin Lesea and Andrew Percey" Negative-Bias Temperature Instability (NBTI) Effects in 90 nm PMOS" XilinxWP224 (v1. 1) November 21, 2005.
- Michael S-C Lu1, Dong-Hang Liu, Li-Sheng Zheng and Sheng-Hsiang Tseng "CMOS micromachined structures using transistors in the subthreshold region for thermal sensing", Journal of micromechanics and microengineering, 2006 pp. 1734-1739.
Index Terms
Keywords