The week's pick
Random Articles
Reseach Article
Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 41 - Number 9 |
| Year of Publication: 2012 |
| Authors: Sudhanshu Mishra, Manoranjan Pradhan |
10.5120/5568-7656
|
Sudhanshu Mishra, Manoranjan Pradhan . Synthesis Comparison of Karatsuba Multiplierusing Polynomial Multiplication, Vedic Multiplier and Classical Multiplier. International Journal of Computer Applications. 41, 9 ( March 2012), 13-17. DOI=10.5120/5568-7656
Abstract
In this paper, the authors have compared the efficiency of the Karatsuba multiplier using polynomial multiplication with the multiplier implementing Vedic mathematics formulae (sutras), specifically the Nikhilam sutra. The multipliers have been implemented using Spartan 2 xc2s200 pq208 FPGA device having speed grade of -6. The proposed Karatsuba multiplier has been found to have better efficiency than the multipliers involving Vedic mathematics formulae.
References
- Chin-Bou Liu, Chua-Huang Huang, and Chin-Laung. Lei, "Design and Implementation of long-digit Karatsuba's multiplication algorithm using tensor product formulation", in Ninth workshop on compiler techniques for high performance computing, 2003, pp. 1-8.
- G. Zhou, H. Michalik, and L. Hinsenkamp, "Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 7, 2010, pp. 1057-1066.
- Z. Dyka and P. Langendoerfer, "Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method", in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (IEEE Computer Society), 2005,1530-1591/05.
- M. Pradhan , R. Panda and S. K. Sahu, "Speed Comparison of 16×16 Vedic Multipliers", International Journal of Computer Applications, Vol. 21, No. 6, 2011, pp. 16-19.
- M. Pradhan , R. Panda and S. K. Sahu, "MAC Implementation using Vedic Multiplication Algorithm", International Journal of Computer Applications, Vol. 21, No. 7, 2011, pp. 26-28.
- A. Weimerskirch and C. Paar, "Generalizations of the Karatsuba algorithm for efficient implementations," 2006. [Online]. Available: http:// eprint. iacr. org/2006/224. pdf
- C. Rebeiro and D. Mukhopadhyay, "Power attack resistant efficient FPGA architecture for Karatsuba multiplier," in 21st International Conference on VLSI Design, 2008, pp. 706–711.
- M. Markovic, T. Unkasevic, and G. Dordevic, "RSA Algorithm Optimization On Assembler Of Ti Tms320c54x Signal Processors", in proceedings of European Association for Signal Processing, 2002. Available at: http://www. eurasip. org/Proceedings/Eusipco/2002/articles/paper189. pdf.
- S. R. Vaidya and D. R. Dandekar, "Performance Comparison of Multipliers for Power-Speed Trade-off in VLSI Design", in 12th International Conference on Networking, VLSI and Signal Processing ,2010, 262-266.
- Leonard Gibson Moses S and Thilagar M, "VLSI Implementation of High Speed DSP algorithms using Vedic Mathematics", International Journal of Computer Communication and Information System, 2010,Vol. 2, No. 1, pp. 119-122.
- Duif, N. 2011 Smart card implementation of a digital signature scheme for Twisted Edwards curves. Master thesis. Student number: 0554878. Department of Mathematics and Computer Science. TechnischeUniversiteit Eindhoven.
- BogdanPasca. 2011. High-performance floating-point computing on reconfigurable circuits. Doctoral thesis. Superior Normal School Of Lyon (ÉcoleNormaleSupérieure De Lyon). Laboratory of Parallel Computing (Laboratoire de l'Informatique du Parallélisme). Graduate School of Mathematics and Computer Science from Lyon.
Index Terms
Keywords