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Design of High-performance Digital Logic Circuits based on FinFET Technology

by V Narendar, Wanjul Dattatray R, Sanjeev Rai, R. A. Mishra
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 41 - Number 20
Year of Publication: 2012
Authors: V Narendar, Wanjul Dattatray R, Sanjeev Rai, R. A. Mishra
10.5120/5812-8104

V Narendar, Wanjul Dattatray R, Sanjeev Rai, R. A. Mishra . Design of High-performance Digital Logic Circuits based on FinFET Technology. International Journal of Computer Applications. 41, 20 ( March 2012), 40-44. DOI=10.5120/5812-8104

@article{ 10.5120/5812-8104,
author = { V Narendar, Wanjul Dattatray R, Sanjeev Rai, R. A. Mishra },
title = { Design of High-performance Digital Logic Circuits based on FinFET Technology },
journal = { International Journal of Computer Applications },
issue_date = { March 2012 },
volume = { 41 },
number = { 20 },
month = { March },
year = { 2012 },
issn = { 0975-8887 },
pages = { 40-44 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume41/number20/5812-8104/ },
doi = { 10.5120/5812-8104 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:30:08.782982+05:30
%A V Narendar
%A Wanjul Dattatray R
%A Sanjeev Rai
%A R. A. Mishra
%T Design of High-performance Digital Logic Circuits based on FinFET Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 41
%N 20
%P 40-44
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Double-gate FinFET is a novel device structure used in the nanometer regime, whereas the conventional CMOS technology's performance deteriorates due to increased short channel effects (SCEs). Double-gate (DG) FinFETs has better SCEs performance compared to the conventional CMOS and stimulates technology scaling. In this paper, we are designing 32nm DGFinFETs and extracting their characteristics by using Sentaurus TCAD, Simulated results of the device show that it can be governed at the nanometer - scale regime. DGFinFET has independent gates; threshold voltage of one gate can be altered by varying the voltage at the other gate. By using this phenomenon logic circuit can be configured in one of the modes such as SG mode, LP mode, IG mode and IG/LP mode. INVERTER and NAND gate are designed in the above mentioned node and comparison has been drawn between them. Based on the simulated results SG-mode is adequate for high-performance design.

References
  1. J. P. Colinge, FinFETs and other Multi-Gate Transistors Springer, 2007.
  2. Z. Lu and J. G. Fossum, "Short-Channel Effects in Independent-Gate FinFETs," IEEE ELECTRON DEVICE LETTERS, vol. 28, no. 2, February 2007.
  3. F. Jafari, M. Mosaffa, and S. Mohammadi, "Designing robust asynchronous circuits based on FinFET technology," IEEE 14th ECDSD, 2011.
  4. M. Rostami, and K. Mohanram, "Dual Vth independent gate FinFETs for low-power logic circuits," IEEE Trans. CAD of Int. Circuits and Systems, vol. 30, no. 3, March 2011.
  5. International Technology Roadmap for Semiconductors 2010 [Online]. Available: http://public. itrs. net
  6. W. Zhang, J. G. Fossum, L. Mathew, and Y. Du, "Physical insights regarding design and performance of independent-gate FinFETs," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2198-2206, oct. 2005.
  7. M. V. R. Reddy, D. K. Sharma, M. B. Patil, and V. R. Rao "Power-area evaluation of various double-gate RF mixer topologies," IEEE Electron Device Letters, vol. 26, no. 9, sept. 2005.
  8. G. Pei and E. C. C. Kan, "Independently driven DG MOSFETs for mixed-signal circuits: Part I?Quasi-static and nonquasi-static channel coupling", IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2086-2093.
  9. J. Gu, J. keane, S. Sapatnekar, and C. Kim, "Width quantization aware FinFET circuit design", in Proc. IEEE CICC, 2006, pp. 337-340.
  10. Mayank Shrivastava, M. S. Baghini, D. K. Sharma, V. R. Rao "A novel bottom spacer FinFET structure for improved short-channel, power-delay, and thermal performance" IEEE Trans. on Electron Devices, vol. 57, no. 6, june 2010, pp. 1287-1294.
  11. "Sentaurus TCAD Manuals", http:// www. synopsys. com
  12. A. Muttreja, N. Agarwal, and N. K. Jha, "CMOS logic design with independent gate FinFETs," in Proc. Int. Conf. Computer Design, Oct. 2007, pp. 560–567.
  13. M. Rostami and K. Mohanram, "Novel dual-Vth independent-gate FinFET circuits," in Proc. Asia South Pacific Design Automation Conf. ,Jan. 2010, pp. 867–872.
  14. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U. K. : Cambridge Univ. Press, 1998.
  15. S. Tawfik and V. Kursun, "Characterization of new static independentgate biased FinFET latches and flip-flops under process variations," in Proc. Int. Symp. Quality of Electronic Design, Mar. 2008, pp. 311–316.
Index Terms

Computer Science
Information Sciences

Keywords

Double-gate Finfet (dgfinfet) High-performance Independent Gate (ig) Mode Logic Gates Low Power (lp) Mode Short Channel Effects (sces) Shorted Gate (sg) Mode

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