We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell

by Ila Gupta, Neha Arora, B. P. Singh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 40 - Number 2
Year of Publication: 2012
Authors: Ila Gupta, Neha Arora, B. P. Singh
10.5120/4930-7161

Ila Gupta, Neha Arora, B. P. Singh . An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell. International Journal of Computer Applications. 40, 2 ( February 2012), 31-36. DOI=10.5120/4930-7161

@article{ 10.5120/4930-7161,
author = { Ila Gupta, Neha Arora, B. P. Singh },
title = { An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell },
journal = { International Journal of Computer Applications },
issue_date = { February 2012 },
volume = { 40 },
number = { 2 },
month = { February },
year = { 2012 },
issn = { 0975-8887 },
pages = { 31-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume40/number2/4930-7161/ },
doi = { 10.5120/4930-7161 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:27:02.821678+05:30
%A Ila Gupta
%A Neha Arora
%A B. P. Singh
%T An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell
%J International Journal of Computer Applications
%@ 0975-8887
%V 40
%N 2
%P 31-36
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A multiplexer, sometimes referred to as a "mux", is a device that selects between a numbers of input signals. It is a combinational logic circuit. It is a unidirectional device and used in any application in which data must be switched from multiple sources to a destination. This paper represents the simulation of different 2:1 Multiplexer Structures and their comparative analysis on different parameters such as power supply voltage, operating frequency, temperature and area efficiency etc and its application in 1 bit full adder cell. All the simulations have been carried out on BSIM 3V3 90nm technology at Tanner EDA tool.

References
  1. Kang, Sung-Mo, Leblebici and Yusuf (1999), “CMOS Digital Integrated Circuits Analysis and Design”, McGraw-Hill International Editions, Boston, 2nd Edition.
  2. Yano, K., Sasaki, Y., Rikino, K. and Seki, K. (1996) “Top-down pass transistor logic design”, IEEE Journal of Solid-State Circuits 31(6), 792–803.
  3. Kiseon Cho and Minkyu Song,” Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique” VLSI Design, 2002 Vol. 14 (3), pp. 249–258.
  4. D. Z. Turker,, S. P.Khatri , “A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications”, IEEE transactions on circuits and systems june 2011, vol. 58, no. 6, pp. 1125-1138.
  5. F-s Lai and W Hwang, “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High-Performance Digital Systems” IEEE journal of solid-state circuits, vol. 32, no. 4, april 1997,pp 563-573.
  6. P. K. Lala and A. Walker, “A Fine Grain Configurable Logic Block for Self-checking FPGAs”,VLSI Design 2001, Vol. 12, No. 4, pp. 527-536.
  7. Jan M. Rabaey, Digital Integrated Circuits; a design prospective, Upper Saddle River: Prentice-Hall, 1996.
  8. Heller, L. G. et al., "Cascode Voltage Switch Logic: A differential CMOS Logic Family", Proceedings of 1984 IEEE International Solid-state Circuits Conference, pp. 16-17.
  9. T. Sharma, Prof. B.P.Singh, K.G.Sharma, N. Arora , “High Speed, Low Power 8T Full Adder Cell with 45% Improvement in Threshold Loss Problem”, Advances in Networking, VLSI and Signal processing pp.272-27.
  10. S. R. Chowdhury, A. Banerjee, A. Roy, H. Saha “A high Speed 8 Transistor Adder Design using Novel 3 Transistor XOR Gates” International Journal of Electronics, Circuits and System s, vol. 2, No. 4, pp.217-223, 2008.
  11. A. Bellaouar, Mohamed I. Elmasry, “Low-power digital VLSI design: circuits and systems”, 2nd Edition.
Index Terms

Computer Science
Information Sciences

Keywords

CMOS Logic Low power Full adder and VLSI

Powered by PhDFocusTM