The week's pick
Random Articles
Reseach Article
Universal Pattern Set for Arithmetic Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 40 - Number 15 |
| Year of Publication: 2012 |
| Authors: Ashok Kumar, Rahul Raj Choudhary, Pooja Bhardwaj, M. S. Dhaka, Rajkumar Choudhary |
10.5120/5060-7390
|
Ashok Kumar, Rahul Raj Choudhary, Pooja Bhardwaj, M. S. Dhaka, Rajkumar Choudhary . Universal Pattern Set for Arithmetic Circuits. International Journal of Computer Applications. 40, 15 ( February 2012), 47-51. DOI=10.5120/5060-7390
Abstract
The exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.
References
- N. Weste and K. Eshragian, “Principles of CMOS VLSI Design”, A Systems Perspective, second ed. Addison-Wesley, 1994.
- M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits", Springer, 2000.
- J. A. Rivers and P. Kudva. “Reliability Challenges and System Performance at the Architecture Level”. IEEE Des. Test, 26(6), pp. 62-73, 2009.
- V.D. Agrawal, C.J. Lin, P. Rutkowski, S. Wu, and Y. Zorian, “Built- In Self-Test for Digital Integrated Circuits”, AT&T Technical J.,pp. 30-39, Mar./Apr. 1994.
- Y. Zorian, A.J. Van de Goor, and I. Schanstra, “An Effective BIST Scheme for Ring-Address Type FIFOs”, Proc. IEEE Int'l Test Conf., pp. 378-387, 1994.
- B. Nadeau-Dostie, A. Silburt, and V.K. Agarwal, “Serial Interfacing for Embedded Memory Testing”, IEEE Design & Test of Computers, vol. 7, no. 2, pp. 52-63, Apr. 1990.
- Y. Zorian and A. Ivanov, “An Effective BIST Scheme for ROMs”, IEEE Trans. Computers, vol. 41, no. 5, pp. 646-653, May 1992.
- T.F.Ngai, M.J.Irwin and S.Rawat, “ Regular area-time efficient carry-look-ahead adders, “Journal of parallel & distributed computing, volume 3, no.3,PP.92-105,1986,
- Nuno Roma and Tiago Dias and Leonel Sousa, “Fast Adder Architecture: Modeling and Experimental Evaluation, R.Alves Redol,9, 1000-029 Lisbon, Portugal.
- C.S. Wallace, “A Suggestion for a Fast Multiplier”, IEEE Trans. Computers, vol. 13, pp. 14-17, Feb. 1964.
- K. Hwang, “Computer Arithmetic: Principles, Architecture and Design”. New York: Wiley, 1978
- A.D. Friedman, “Easily Testable Iterative Systems”, IEEE Trans. In Computers, vol. 22, no. 12, pp. 1,061-1,064, Dec. 1973.
- J.P. Shen and F.J. Ferguson, “The Design of Easily Testable VLSI Array Multipliers”, IEEE Trans. Computers, vol. 33, no. 6, pp. 554- 560, June 1984.
- A.R. Takach and N.K. Jha, “Easily Testable Gate Level and DCVS Multipliers”, IEEE Trans. Computer-Aided Design, vol. 10, no. 7, pp. 932-942, July 1991.
- A. Chatterjee and J.A. Abraham, “Test Generation for Arithmetic Units by Graph Labeling”, Proc. FTCS 17, pp. 284-289, Pittsburgh, Pa., July 1987.
- S.J. Hong, “The Design of a Testable Parallel Multiplier”, IEEE Trans. Computers, vol. 39, no. 3, pp. 411-416, Mar. 1990
- Dimitris Gizopoulos, Antonis Paschalis and Yervant Zorian, “An Effective Built-In Self-Test Scheme For Parallel Multipliers”, IEEE Transactions On Computers, Vol. 48, No. 9, September 1999.
- A. Chatterjee and J.A. Abraham, “Test Generation, Design-for- Testability and Built-In Self-Test for Arithmetic Units Based on Graph Labeling”, J. Electronic Testing: Theory and Applications, vol. 2, pp. 351-372, 1991.
- E.M. Abdoulhamid and E. Cerny, “Built In Testing of Unilateral Iterative Arrays”, IEEE Trans. Computers, vol. 33, pp. 560-564, June 1984.
- Y. Tian, M. Mercer, W. Shi, and M. Grimaila. “An optimal test pattern selection method to improve the defect coverage”. In Proc. of IEEE ITC, 2005.
- Z. Wang and K. Chakrabarty. “An efficient test pattern selection method for improving defect coverage with reduced test data volume and test application time”. In Proc. of IEEE Asian Test Symp. 2006, pages 333–338.
- Anu Gupta, “Design explorations of VLSI arithmetic circuits, “BITS Pilani, ID No.1995PHXF405.
Index Terms
Keywords