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A Novel Latch design for Low Power Applications

by Abhilasha, K. G. Sharma, Tripti Sharma, B. P. Singh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 39 - Number 16
Year of Publication: 2012
Authors: Abhilasha, K. G. Sharma, Tripti Sharma, B. P. Singh
10.5120/4907-7420

Abhilasha, K. G. Sharma, Tripti Sharma, B. P. Singh . A Novel Latch design for Low Power Applications. International Journal of Computer Applications. 39, 16 ( February 2012), 34-39. DOI=10.5120/4907-7420

@article{ 10.5120/4907-7420,
author = { Abhilasha, K. G. Sharma, Tripti Sharma, B. P. Singh },
title = { A Novel Latch design for Low Power Applications },
journal = { International Journal of Computer Applications },
issue_date = { February 2012 },
volume = { 39 },
number = { 16 },
month = { February },
year = { 2012 },
issn = { 0975-8887 },
pages = { 34-39 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume39/number16/4907-7420/ },
doi = { 10.5120/4907-7420 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:26:47.493409+05:30
%A Abhilasha
%A K. G. Sharma
%A Tripti Sharma
%A B. P. Singh
%T A Novel Latch design for Low Power Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 39
%N 16
%P 34-39
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes novel design of 8-transistor latch. Design comparison with the conventional design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient latch design is better choice for portable applications.

References
  1. <ul style="text-align: justify;"> A. Wang, B. H. Calhoun and A. Chandrakasan, “Sub-threshold design for ultra low-power systems”. Springer publishers, 2005. J.-J. Kim and K. Roy, “Double gate-MOSFET subthreshold circuit for ultra low power applications,” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1468–1474, Sep. 2004. M. Sinangil, N. Verma, and A. Chandrakasan, “A reconfigurable 65nm SRAM achieving voltage scalability from 0.25–1.2 V and performance scalability from 20 kHz–200 MHz,” in Pr
Index Terms

Computer Science
Information Sciences

Keywords

Level converting Flip Flop Portable Applications Latch Sub-threshold Region and Low Power applications

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