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Reseach Article

FPGA Implementation of Voltage Sharing Strategy for Series Connected SEPICS

by A. Ezhilarasi, M. Ramaswamy
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 39 - Number 14
Year of Publication: 2012
Authors: A. Ezhilarasi, M. Ramaswamy
10.5120/4887-7375

A. Ezhilarasi, M. Ramaswamy . FPGA Implementation of Voltage Sharing Strategy for Series Connected SEPICS. International Journal of Computer Applications. 39, 14 ( February 2012), 11-18. DOI=10.5120/4887-7375

@article{ 10.5120/4887-7375,
author = { A. Ezhilarasi, M. Ramaswamy },
title = { FPGA Implementation of Voltage Sharing Strategy for Series Connected SEPICS },
journal = { International Journal of Computer Applications },
issue_date = { February 2012 },
volume = { 39 },
number = { 14 },
month = { February },
year = { 2012 },
issn = { 0975-8887 },
pages = { 11-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume39/number14/4887-7375/ },
doi = { 10.5120/4887-7375 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:26:26.815483+05:30
%A A. Ezhilarasi
%A M. Ramaswamy
%T FPGA Implementation of Voltage Sharing Strategy for Series Connected SEPICS
%J International Journal of Computer Applications
%@ 0975-8887
%V 39
%N 14
%P 11-18
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The paper orients to develop a strategy, with a view to ensure that the output voltage is equally shared among a number of Single Ended Primary Inductance Converters (SEPICs), in addition to ensuring regulation of the load voltage. It attempts to exploit the robustness of a Variable Structure Controller (VSC) to offset the circuit parasitic and extract a stable output irrespective of the variations in input voltage, circuit parameters and/or load. The methodology envisages characterizing the desired time response and acclaiming an acceptable steady state and transient results. It involves the use of a Field Programmable Gate Array (FPGA) to implement the proposed scheme and illustrate its practical viability. The performance evaluated through MATLAB based simulation is adequately validated using a suitable prototype to project its applicability over a preferred operating range.

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Index Terms

Computer Science
Information Sciences

Keywords

SEPIC VSC Voltage sharing Time response FPGA