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Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios

by Bindiya Kamboj, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 37 - Number 10
Year of Publication: 2012
Authors: Bindiya Kamboj, Rajesh Mehra
10.5120/4645-6714

Bindiya Kamboj, Rajesh Mehra . Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios. International Journal of Computer Applications. 37, 10 ( January 2012), 25-29. DOI=10.5120/4645-6714

@article{ 10.5120/4645-6714,
author = { Bindiya Kamboj, Rajesh Mehra },
title = { Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios },
journal = { International Journal of Computer Applications },
issue_date = { January 2012 },
volume = { 37 },
number = { 10 },
month = { January },
year = { 2012 },
issn = { 0975-8887 },
pages = { 25-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume37/number10/4645-6714/ },
doi = { 10.5120/4645-6714 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:23:59.192692+05:30
%A Bindiya Kamboj
%A Rajesh Mehra
%T Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios
%J International Journal of Computer Applications
%@ 0975-8887
%V 37
%N 10
%P 25-29
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper an efficient approach is presented to design and implement Direct Digital Frequency Synthesizer (DDFS) with high speed and spectral purity for wireless applications like Software Defined Radio (SDR). The implementation is based upon efficient utilization of embedded slices and LUT’s of the target device to enhance the speed of the proposed design. The proposed DDFS is designed & simulated with MATLAB and Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST) and implemented on Spartan 3E & Virtex 2P based XC3S500E and XC2VP307FF896 FPGA target device respectively. The proposed design can operate at an estimated frequency of 116.2 MHz and 146.5 MHz, along with the minimum period of 8.605 ns and 6.8240 ns for the Spartan 3e and Virtex 2 Pro FPGA device, respectively. The FFT analysis of developed DDFS shows enhanced SFDR of 86.17dB.

References
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Index Terms

Computer Science
Information Sciences

Keywords

DDFS FFT FPGA SDR and SFDR.

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