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Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 36 - Number 12 |
| Year of Publication: 2011 |
| Authors: A. Sathish, Dr. M. Madhavi Latha, Dr. K. Lal Kishore |
10.5120/4546-6346
|
A. Sathish, Dr. M. Madhavi Latha, Dr. K. Lal Kishore . Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus. International Journal of Computer Applications. 36, 12 ( December 2011), 7-11. DOI=10.5120/4546-6346
Abstract
In Deep-submicron (DSM) systems, the crosstalk effect on on-chip data buses and interconnects dictates the overall performance and reliability of the highly integrated systems. In many digital processors and SoC the reliable transfer of the information over the data bus is crucial for the proper operation of a particular system. Hence ECC techniques are used on data buses for reliable transfer of the information. Employing the ECC on data buses eventually increases the switching activity that affects the power consumption and delay of the system. Reducing the power dissipation of the VLSI chip is one of the major challenges in the DSM technology. One of the best techniques to reduce the transitions is to use encode and decoder along with the ECC on the data bus. Hence an efficient switching activity reduction technique is proposed for fault tolerant data bus which can reduce the overall transitions. The proposed encoding technique reduces the switching activity by 18% to 22.5%. Its efficiency is 8% to 15% more compare to others encoding techniques.
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