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Hardware Implementation of FFT using Vertically and Crosswise Algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 35 - Number 1 |
| Year of Publication: 2011 |
| Authors: Nidhi Mittal, Abhijeet Kumar |
10.5120/4365-6020
|
Nidhi Mittal, Abhijeet Kumar . Hardware Implementation of FFT using Vertically and Crosswise Algorithm. International Journal of Computer Applications. 35, 1 ( December 2011), 17-20. DOI=10.5120/4365-6020
Abstract
This paper is devoted for the implementation of FFT, which uses Vertical and Crosswise algorithms. Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. But the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem UrdhvaTirvagbhyam in Vedic mathematics is an efficient method of multiplication. It literally means “Vertically and crosswise”. It is based on a novel concept through which the generation of all partial products can be done and then, concurrent addition of these partial products can be done. It is one of the sutra of Vedic Mathematics equally applicable to all cases of multiplication. The conventional multiplication method requires more time & area on silicon than Vedic algorithms. In this paper the design for the architecture of FFT using Vertically and Crosswise is proposed and described using Verilog hardware description language. The code description is simulated using ModelSim SE 5.7f and synthesized using ISE Xilinx 9.2i for the FPGA device Spartan XC3S500e-fg320, Speed Grade-4. The results show how by combining these two approaches proposed design methodology is time, area and power efficient.
References
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