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Encoding SystemC Models in Formal Synchronous Formalism

by Riadh Hocine, Hamoudi Kalla
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 34 - Number 3
Year of Publication: 2011
Authors: Riadh Hocine, Hamoudi Kalla
10.5120/4080-5876

Riadh Hocine, Hamoudi Kalla . Encoding SystemC Models in Formal Synchronous Formalism. International Journal of Computer Applications. 34, 3 ( November 2011), 26-32. DOI=10.5120/4080-5876

@article{ 10.5120/4080-5876,
author = { Riadh Hocine, Hamoudi Kalla },
title = { Encoding SystemC Models in Formal Synchronous Formalism },
journal = { International Journal of Computer Applications },
issue_date = { November 2011 },
volume = { 34 },
number = { 3 },
month = { November },
year = { 2011 },
issn = { 0975-8887 },
pages = { 26-32 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume34/number3/4080-5876/ },
doi = { 10.5120/4080-5876 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:20:09.653555+05:30
%A Riadh Hocine
%A Hamoudi Kalla
%T Encoding SystemC Models in Formal Synchronous Formalism
%J International Journal of Computer Applications
%@ 0975-8887
%V 34
%N 3
%P 26-32
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The size and thus the complexity of many systems, that use an intellectual property component (IP), have reached a level where design validation with mere testing and simulation does not deliver the required quality any more. Obtaining a formal model from a non-formal one is a complex and error prone task. A logical step is therefore to try to generate automatically a formal description from an existing non-formal system model, thus making this step faster and more reliable. In this paper, we describe a methodology to automaticallygenerate formal synchronous models from existing non-formalsystem level design descriptions that integrates smoothly intoexisting co-design flows. We exemplify the approach with thepopular system design language SystemC and the flexible andexpressive synchronous dataflow formalism SIGNAL.SystemC is a HDL which allows for modeling systems in behavioral level, it is a set of library routines and macros implemented in C++, it is a good language for input of design flow for the systems which requires verification, but it is not a formal language.

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Index Terms

Computer Science
Information Sciences

Keywords

SystemC SIGNAL Pointers Analysis Static Single Assignment Functional and Compositional Correctness

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