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Reseach Article

VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs

by S. Sahnoun, N. Masmoudi, H. Levi
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 33 - Number 8
Year of Publication: 2011
Authors: S. Sahnoun, N. Masmoudi, H. Levi
10.5120/4041-5790

S. Sahnoun, N. Masmoudi, H. Levi . VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs. International Journal of Computer Applications. 33, 8 ( November 2011), 24-27. DOI=10.5120/4041-5790

@article{ 10.5120/4041-5790,
author = { S. Sahnoun, N. Masmoudi, H. Levi },
title = { VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs },
journal = { International Journal of Computer Applications },
issue_date = { November 2011 },
volume = { 33 },
number = { 8 },
month = { November },
year = { 2011 },
issn = { 0975-8887 },
pages = { 24-27 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume33/number8/4041-5790/ },
doi = { 10.5120/4041-5790 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:19:40.160760+05:30
%A S. Sahnoun
%A N. Masmoudi
%A H. Levi
%T VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs
%J International Journal of Computer Applications
%@ 0975-8887
%V 33
%N 8
%P 24-27
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this work, we expose our approach to design and optimize mixed analogue and digital systems at a high level description using the hardware description language VHDL-AMS. Many statistical experimental design methods are employed in optimization. We apply Hocke_D4 experimental designs with five parameters in order to minimize the lock time and the spurious level of a fractional-N synthesizer acting as a direct MSK modulator and designed for the DECT standard application.

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Index Terms

Computer Science
Information Sciences

Keywords

Hierarchical design VHDL-AMS description MSK modulator Fractional-N synthesizers Optimization Experimental designs Lock time Spurious level.