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Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation

by Vandana S. Shah, Dr. R. V. Kshirsagar
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 32 - Number 3
Year of Publication: 2011
Authors: Vandana S. Shah, Dr. R. V. Kshirsagar
10.5120/3953-5432

Vandana S. Shah, Dr. R. V. Kshirsagar . Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation. International Journal of Computer Applications. 32, 3 ( October 2011), 50-55. DOI=10.5120/3953-5432

@article{ 10.5120/3953-5432,
author = { Vandana S. Shah, Dr. R. V. Kshirsagar },
title = { Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation },
journal = { International Journal of Computer Applications },
issue_date = { October 2011 },
volume = { 32 },
number = { 3 },
month = { October },
year = { 2011 },
issn = { 0975-8887 },
pages = { 50-55 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume32/number3/3953-5432/ },
doi = { 10.5120/3953-5432 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:18:14.655263+05:30
%A Vandana S. Shah
%A Dr. R. V. Kshirsagar
%T Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation
%J International Journal of Computer Applications
%@ 0975-8887
%V 32
%N 3
%P 50-55
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Present title discloses a distinctive method to cram the processor behavior while dealing with the multifaceted task of matrix manipulation. System facilitates this distinct feature by allowing user to input the data in suitable form and observe the output using suitable display devices. [5] System is build around high performance VLSI technology. Matrix manipulation is on the whole parallel architecture of logical expressions. VLSI when implemented using High Performance Gate Arrays becomes most suitable for implementing parallel architecture. [6]

References
  1. Kuan Jen Lin, Yi Tang Chiu and Shan Chief Fang,“Design Optimization and Automation for Secure Cryptographic Circuits”, 22nd International conference on VLSI, 5-9 Jan.2009 , New Delhi,India.
  2. FPGA prototyping by VHDL Examples: Xilinx Spartan-3 Version, e-book, 2008.
  3. Arifur Rahman, “FPGA based design and applications”, Springer edition, July 2008.
  4. Morris Mano, “Digital Logic and Computer Design- Advanced Digital Design fundamentals and Issues” Prentice Hall , 2003.
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  13. PLA (programmable logic array) available at http://tams-www.informatik.uni hamburg.de/applets/hades/webdemos/42- programmable/10-pla/pla.html
  14. The Datasheet Archive http://www.datasheetarchive.com/XC2S100PQ2 08-5C-datasheet.html
  15. http://www.national.com In System Programming Communication Protocol, revision 2.
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  17. Dot Matrix Liquid Crystal Display Controller/Driver http://www.adafruit.com/datasheets/HD44780.pdf
Index Terms

Computer Science
Information Sciences

Keywords

VLSI Gate Arrays Parallel Architecture Matrix Manipulation

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