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Article:A Survey of High-Level Synthesis Techniques for Area, Delay and Power Optimization
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 32 - Number 10 |
| Year of Publication: 2011 |
| Authors: S.M. Logesh, D. S. Harish Ram, M.C. Bhuvaneswari |
10.5120/3935-3952
|
S.M. Logesh, D. S. Harish Ram, M.C. Bhuvaneswari . Article:A Survey of High-Level Synthesis Techniques for Area, Delay and Power Optimization. International Journal of Computer Applications. 32, 10 ( October 2011), 1-6. DOI=10.5120/3935-3952
Abstract
With increasing complexity of digital signal processing VLSI circuits in recent decades, design methodologies and tools have moved to higher abstraction levels. High level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power of the circuit are mutually conflicting thereby necessitating trade-offs between different objectives. The electronic system-level (ESL) paradigm facilitates exploration, synthesis, and verification that can handle the complexity of today’s system-on-chip (SoC) designs. Processor customization and High Level Synthesis have become necessary paths to efficient ESL design. This paper presents the survey of high level synthesis approaches and methodologies for simultaneous area, delay and power optimization.
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