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Hardware Acceleration of Histogram Equalization and Image Sharpening Filter on NIOS-II Processor Based SOC on FPGA

by Ramakrishna.M, Kishore Kumar.M, Addanki Purna Ramesh
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 31 - Number 1
Year of Publication: 2011
Authors: Ramakrishna.M, Kishore Kumar.M, Addanki Purna Ramesh
10.5120/3957-5401

Ramakrishna.M, Kishore Kumar.M, Addanki Purna Ramesh . Hardware Acceleration of Histogram Equalization and Image Sharpening Filter on NIOS-II Processor Based SOC on FPGA. International Journal of Computer Applications. 31, 1 ( October 2011), 48-54. DOI=10.5120/3957-5401

@article{ 10.5120/3957-5401,
author = { Ramakrishna.M, Kishore Kumar.M, Addanki Purna Ramesh },
title = { Hardware Acceleration of Histogram Equalization and Image Sharpening Filter on NIOS-II Processor Based SOC on FPGA },
journal = { International Journal of Computer Applications },
issue_date = { October 2011 },
volume = { 31 },
number = { 1 },
month = { October },
year = { 2011 },
issn = { 0975-8887 },
pages = { 48-54 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume31/number1/3957-5401/ },
doi = { 10.5120/3957-5401 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:17:02.505508+05:30
%A Ramakrishna.M
%A Kishore Kumar.M
%A Addanki Purna Ramesh
%T Hardware Acceleration of Histogram Equalization and Image Sharpening Filter on NIOS-II Processor Based SOC on FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 31
%N 1
%P 48-54
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, we presents a framework for hardware accelerating methods for video post processing system implemented on FPGA. The histogram equalization and image-sharpening filter are the algorithms ported onto the SOC having Altera NIOS-II soft processor. Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Saturation and the Histogram are the new instructions added to the processor that are implemented in hardware and interfaced to the NIOS-II processor. The software implementation of the algorithms has been modified to use the new instructions added for computing the saturation and histogram calculation. Performance of the software implementation of the histogram equalization and sharpening algorithms is boosted by these new instructions added to the NIOS-II processor. The comparison shows that the implemented tasks have been accelerated by “multiple” times. The saturation instruction is generic instruction, which can be used in many Image processing applications. The benefit of speed is obtained at the cost of very small hardware resources.

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Index Terms

Computer Science
Information Sciences

Keywords

Histogram equalization SOC NIOS-II soft processor FPGA

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