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VLSI Implementation of Adders for High Speed ALU
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 29 - Number 10 |
| Year of Publication: 2011 |
| Authors: Prashant Gurjar, Rashmi Solanki, Pooja Kansliwal, Mahendra Vucha |
10.5120/3601-5002
|
Prashant Gurjar, Rashmi Solanki, Pooja Kansliwal, Mahendra Vucha . VLSI Implementation of Adders for High Speed ALU. International Journal of Computer Applications. 29, 10 ( September 2011), 11-15. DOI=10.5120/3601-5002
Abstract
This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU). Design of a high speed single core processor is the future goal of this paper. Single core processor would have many advantages over a multiple-core approach. Task execution on a single core is a well understood process, while execution on many cores is a problem that has not yet been solved. There are also computational tasks which parallelize very badly, where a single high clock rate processor would suit them very well. Such a high speed processor needs certain components that should support high speed. The two main components of processors are the ALU and the register file. The one of the critical path within an ALU may be the carry-chain in addition operation. In this research article, we have simulated and synthesized the various adders like full adder, ripple carry adder, carry-look ahead adder, carry-skip adder and carry –select adder by using VHDL and Xilinx ISE 9.2i. The simulated results are verified and the functionality of high speed adders and the parameters like area and speed is analyzed. Finally this paper concludes that the carry-skip adder is the more efficient in speed and area consumption.
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