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Enhanced Leakage Control in Scaled 45nm nMOS Devices using SiO2 and Si3N4
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 29 - Number 1 |
| Year of Publication: 2011 |
| Authors: Subhra Dhar, Manisha Pattanaik, P.Rajaram |
10.5120/3531-4817
|
Subhra Dhar, Manisha Pattanaik, P.Rajaram . Enhanced Leakage Control in Scaled 45nm nMOS Devices using SiO2 and Si3N4. International Journal of Computer Applications. 29, 1 ( September 2011), 5-7. DOI=10.5120/3531-4817
Abstract
Gate-leakage reduction is the key motivation for the replacement of SiO2 with alternative gate dielectrics. 45nm gate length scaled grooved and bulk nMOSFETs are evaluated to bring out the most compatible and power saving dielectric option using Si3N4 and SiO2 using Silvaco ATLAS device simulator. At the scaled thickness, SiO2 controls the leakage better than Si3N4, whereas at increased thickness of the dielectric Si3N4 proves better for the field scaled grooved and bulk devices with enhanced subthreshold slopes of 51.3mv/dec and 70mv/dec respectively. The field scaled device grooved at single sharp corner may be used for HP applications whereas field scaled bulk device may be used for LP and LSTP applications. This work can be helpful to device engineers working towards achieving ultra low power applications.
References
- Hsing-Huang Tseng, 2010 “The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies” Solid State Circuit Technologies, pp: 462-494
- Brice Tavel, 2004 “Gate dielectric impact for the 65nm Digital and Mixed Signal Platform Applications” Philips Semiconductors, Crolles2Alliance, Crolles, France
- Chris Auth, et al 2008 “45nm High-k+Metal Gate Strain-Enhanced Transistors”, Intel Technology Journal, Vol. 12, Issue 2, , pp-77-87
- Thomas Skotnicki et al. 2008. “Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia” IEEE Transactions on Electron Devices, January 2008, pp: 96-130
- Subhra Dhar, Manisha Pattanaik, P. Rajaram. 2011. “Advancement in Nanoscale CMOS Device Design en route to Ultra Low Power Applications” VLSI Design, Hindawi Publishing Corporation, 2011
- Subhra Dhar, Manisha Pattanaik, P. Rajaram, 2011. “Analyzing ION/IOFF in Ultra Deep Submicron CMOS Devices using Grooved nMOSFETs for low power applications” International Journal of Signal and Imaging Systems Engineering, 2011, in press
- P.H.Bricout, E.Dubois, 1996 “Short Channel Effect Immunity and Current Capability of Sub 0.1micron MOSFETS’s using a Recessed Channel”, IEEE Trans. on Electron Devices, Vol. 43 , No. 8, pp.1251-1254.
- K. Rajendran, W.Schoenmaker, 2001 “Modelling of minimum surface potential and sub threshold swing for grooved gate MOSFETs” Microelectronics Journal, pp.631-639.
- Chia Yeo, Tsu-Jae King, and Chenming Hu. 2003. “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations“, IEEE Transactions on Electron Devices, APRIL 2003, pp: 1027-1035
- Fauziyah Salehuddin, Ibrahim Ahmad, Fazrena Azlee Hamid,, Azami Zaharim, 2009 “Application of Taguchi Method in Optimization of Gate Oxide and Silicide Thickness for 45nm NMOS Device”, International Journal of Engineering & Technology Vol: 9 No: 10, , pp-94-98
- J. Robertson, 2004, “High dielectric constant oxides” Eur. Phys. J. Appl. Phys, 28, pp: 265-291.
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