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Performance Evaluation of Bypassing Array Multiplier with Optimized Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 28 - Number 5 |
| Year of Publication: 2011 |
| Authors: N.Ravi, Dr.T.S.Rao, Dr.T.J.Prasad |
10.5120/3387-4701
|
N.Ravi, Dr.T.S.Rao, Dr.T.J.Prasad . Performance Evaluation of Bypassing Array Multiplier with Optimized Design. International Journal of Computer Applications. 28, 5 ( August 2011), 1-5. DOI=10.5120/3387-4701
Abstract
In this paper a new method is proposed to reduce power and area of the array multiplier. In the proposed method vector merging final adder is removed at final stage of the multiplier, at the final stage the generated carry is given to the input of the column of top adder. The adders also do the same what the vector merging final adder can do. The method is applied for array multiplier and column bypassing multiplier (CBM). The results are carried out by H-Spice with different TSMC (Standard and PTM) technology files at a supply voltage 2.0V. Array multiplier has shown 13.91% and Proposed Column Bypassing Multiplier (PCBM) shown 23.38% less power consumption for 180nm CMOS technology than the conventional array multiplier and CBM. 14-T full adder is used to design the multipliers. Due to elimination of the final adder proposed method saves 56 transistors and cause low area.
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