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Architectural Analysis of RSA Cryptosystem on FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 26 - Number 8 |
| Year of Publication: 2011 |
| Authors: Vibhor Garg, V. Arunachalam |
10.5120/3124-4299
|
Vibhor Garg, V. Arunachalam . Architectural Analysis of RSA Cryptosystem on FPGA. International Journal of Computer Applications. 26, 8 ( July 2011), 30-34. DOI=10.5120/3124-4299
Abstract
This paper presents different architectures in FPGA based implementations of a public key crypto algorithm - RSA algorithm. A hardware-based cryptographic system is preferred as it provides - better security, integrity and is resistant to power analysis attacks [1]. After the complete cryptosystem is simulated in VERILOG [8] and synthesized for specific XILINX FPGAs, the architecture of the cryptosystem is evolved by performing scheduling in the Data Flow Graph. This way there are two types of architectures realized: – one with high concurrency (which takes lesser number of clock cycles) and the other with maximum sequential operations. Subsequently the size of the key is extended and its effects on the architecture, with respect to area and power consumed, are observed. Finally trade-off analysis of the various implementations is done.
References
- S.S. Ghoreishi, M.A. Pormina, H. Bozorgi, and M. Dousti, “High Speed RSA Implementation Based on Modified Booth’s Technique and Montgomery’s Multiplication for FPGA Platform,” in Second International Conference on Advances in Circuits, 2009.
- T. Blum and C. Paar, “High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware,” in IEEE Transactions on Computer, Vol. 50, no. 7, pp. 759-764, July 2001, ISSN: 0018-9340.
- Yachao Zhou and Xiaojun Wang, “An improved implementation of Montgomery Algorithm using efficient pipelining and structured parallelism techniques,” in IET Irish Signals and Systems Conference (ISSC 2010), pp. 7 – 11, June 2010.
- Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, “Efficient Algorithms,” Handbook of Applied Cryptography, pp. 606-609,613-620, June 1996.
- Gang Quan, “Data Flow Graph Intro,” Maseeh College of Engineering and Computer Science, Portland State University, http://web.cecs.pdx.edu/~mperkows/temp/JULY/data-flow-graph.pdf .
- John Fry and Martin Langhammer, “RSA and Public Key Cryptography in FPGAs,” Altera Corporation, Tech. Rep., 2005, pp.1-3.
- Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, SunSoft Press, 1996.
- William Stallings, Cryptography and Network Security Principals and Practices, 4th edition, Pearson Education, Inc., 2006, ISBN 81-7758-774-9.
- Omar Nibouche, Mokhtar Nibouche, Ahmed Bouridane, and Ammar Belatreche, “Fast architectures for FPGA-based implementation of RSA encryption algorithm,” in IEEE International Conference on Field-Programmable Technology, 2004.
- T. Jebelean, “Comparing several GCD algorithms,” in 11th Symposium on Computer Arithmetic, 1993, Proceedings, pp. 180 – 185, 1993, ISBN: 0-8186-3862-1.
- John D. Carpinelli, Computer Systems Organization and Architecture, Pearson Education, Inc., 2001, pp. 353-357, ISBN 81-7808-268-3.
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