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Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 26 - Number 3 |
| Year of Publication: 2011 |
| Authors: Mahendra Vucha, Arvind Rajawat |
10.5120/3084-4222
|
Mahendra Vucha, Arvind Rajawat . Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication. International Journal of Computer Applications. 26, 3 ( July 2011), 18-22. DOI=10.5120/3084-4222
Abstract
The evolution of computer and Internet has brought demand for powerful and high speed data processing, but in such complex environment fewer methods can provide perfect solution. To handle above addressed issue, parallel computing is proposed as a solution to the contradiction. This paper provides solution for the addressed issues of demand for high speed data processing. This paper demonstrates an effective design for the Matrix Multiplication using Systolic Architecture on Reconfigurable Systems (RS) like Field Programmable Gate Arrays (FPGAs). Here, the systolic architecture increases the computing speed by combining the concept of parallel processing and pipelining into a single concept. Here, the RTL code is written for matrix multiplication with systolic architecture and matrix multiplication without systolic architecture in Verilog HDL, compiled and simulated by using Modelsim XE III 6.4b, Synthesized by using Xilinx ISE 9.2i and targeted to the device xc3s500e-5-ft256 and then finally the designs are compared to each other to evaluate the performance of proposed architecture. The proposed Matrix Multiplication with systolic architecture is enhances the speed of matrix multiplication by twice of conventional method.
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