The week's pick
Reseach Article
VHDL Implementation of GCD Processor with Built in Self Test Feature
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 25 - Number 2 |
| Year of Publication: 2011 |
| Authors: Rekha Devi, Jaget Singh, Mandeep Singh |
10.5120/3000-4034
|
Rekha Devi, Jaget Singh, Mandeep Singh . VHDL Implementation of GCD Processor with Built in Self Test Feature. International Journal of Computer Applications. 25, 2 ( July 2011), 50-54. DOI=10.5120/3000-4034
Abstract
The Very Large Scale Integration (VLSI) has a dramatic impact on the growth of digital technology. VLSI has not only reduced the size and the cost, but also increased the complexity of the circuits. Due increase there is a problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. One solution to this problem is to add logic to the IC so that it can test itself. In this paper we have design GCD (greatest common divider) processors in VHDL with BIST capability and compared the area overhead of with and without BIST.
References
- Bushnell M. L. and Agrawal V. D.(2000) Essentials of Electronic Testing. Kluwer Academic Publishers.
- Mohd Yamani Idna Idris “A VHDL Implementation Of UART design with BIST capability” Malaysian Journal of Computer Science, Vol. 19 (1), 2006
- S. Wang, “Generation of low power dissipation and high fault coverage patterns for scan-based BIST”, Proceeding of International Test Conference, 2002, pp. 834 –843.
- Z. Navabi, “VHDL Analysis and Modeling of Digital Systems”, McGraw-Hill Inc., 1991.
- Charles E. Stroud “A Designer's Guide to Built-in Self- Test” Kluwer Academic Publishers 2002
- C. H. Roth “ Digital System Design Using VHDL” PWS Publishing Company, 1998
- D.A. Shalangwa and S. Samaila , “design of a mealy state machine to realized the GDC of Two Numbers”, journal of engineering and Applied Sceinces 4(5-6) pp 338
- Crouch, A. (1999), “Design-for-test for Digital IC’s and Embedded Core Systems”, Prentice Hall, 347 pp
- Pou-Yah Wu & Julian Chuen-Liang Chen, “Parallel Extended GCD Algorithm” Parallel Processing Symposium, 1994.
- Singh, B.; Khosla, A.; Bindra, S.; , "Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST," Advance Computing Conference IACC IEEE International., vol., no., pp.311-314, 6-7 March 2009
- Shikha Kakar, Balwinder Singh, and Arun Khosla” Implementation of BIST Capability using LFSR Techniques in UART” International Journal of Recent Trends in Engineering (IJRTE), Volume 1, Number 3, May 2009 Issue on Electrical & Electronics Page(s): 301-304.
Index Terms
Keywords