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Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 24 - Number 8 |
| Year of Publication: 2011 |
| Authors: Shekar Babu M, Sumanth Kumar Reddy, S V V Sateesh |
10.5120/2971-3995
|
Shekar Babu M, Sumanth Kumar Reddy, S V V Sateesh . Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC. International Journal of Computer Applications. 24, 8 ( June 2011), 26-29. DOI=10.5120/2971-3995
Abstract
As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.
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