The week's pick
Reseach Article
Reduction of Power Dissipation in Logic Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 24 - Number 6 |
| Year of Publication: 2011 |
| Authors: Sreenivasa Rao Ijjada, B.Ramparamesh, Dr. V.Malleswara Rao |
10.5120/2962-3946
|
Sreenivasa Rao Ijjada, B.Ramparamesh, Dr. V.Malleswara Rao . Reduction of Power Dissipation in Logic Circuits. International Journal of Computer Applications. 24, 6 ( June 2011), 10-14. DOI=10.5120/2962-3946
Abstract
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic. In this technique both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors. Leakage current flowing through the NMOS transistor stack reduces due to the increase in the source to substrate voltage in the top NMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor Leakage current flowing through the PMOS transistor stack reduces due to the increase in the source to substrate voltage in the top PMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 180nm.
References
- 2007 International Technology Roadmap for Semiconductors,
- online Available http://public.itrs.net.
- J.Abraham, “Overcoming timing, power bottlenecks,” EE Times, April 2003.
- P. Elakkumanan, C. Thondapu, and R. Sridhar, “A Gate Leakage Reduction Strategy for Sub-70nm Memory Circuit,” in Proceedings of 2004 IEEE Dallas/CAS Workshop, 2004, pp. 145-148.
- Z. Chen, M. Johnson, L. Wei and K. Roy, ‘Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modelling of Transistor Stacks,’ International Symposium on low Power Electronics and Design, pp. 239-244, August 1998.
- S. Dutta, S. Nag, K. Roy, “ASAP: A Transistor Sizing tool for speed, area, and power optimization of static CMOS circuits”, IEEE International Symposium on Circuits and Systems, pp. 61-64, June, 1994
- N. Azizi and F.N. Najm, “An Asymmetric SRAM cell to lower gate leakage,” in Proceedings of 5th IEEE International Symposium on Quality Electronic Design, 2004, pp. 534-539.
- J.Rabaey, “Digital Integrated Circuits, A Design Perspective”, Prentice Hall, Upper Saddle River, NJ, 1996.
- K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design”, Wiley Publishers, New York, 2000.
- B. Yu et al., “Limits of gate oxide scaling in nano-transistors,” in Proceedings of Symposium on VLSI Technology, pp. 90-91, 2000
- “Low Power CMOS Inverter design at different Technologies” International journal of applied engineering research, Dindigul Volume 1, No 3, 201010. “Low Power CMOS Inverter design at different Technologies” International journal of applied engineering research, Dindigul Volume 1, No 3, 2010
- M. C. Johnson, D. Somasekhar, L. Y. Chiou, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” IEEE Trans. VLSI Syst., vol. 10, pp. 1–5, Feb. 2002
- C. Gopalakrishnan and S. Katkoori, “Resource allocation and binding approach for low leakage power,” in Proc. IEEE Int. Conf. VLSI Design, Jan. 2003, pp. 297–302
- S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. P. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” Proc. IEEE ISLPLED, pp. 195–200, Aug. 2001.
- J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. 34th DAC, 1997, pp. 409–414.
Index Terms
Keywords