International Journal of Computer Applications |
Foundation of Computer Science (FCS), NY, USA |
Volume 24 - Number 4 |
Year of Publication: 2011 |
Authors: Sunil Kr. Singh, R. K. Singh, M. P. S. Bhatia |
10.5120/2935-3890 |
Sunil Kr. Singh, R. K. Singh, M. P. S. Bhatia . CAD Optimization Technique in Reconfigurable Computing System using Hybrid Architecture. International Journal of Computer Applications. 24, 4 ( June 2011), 50-54. DOI=10.5120/2935-3890
Design automation or computer-aided design (CAD) for reconfigurable computing system is giving a new concept of research and development in system design for present and future technological environment. The basic ability of reconfigurable computing is to perform computations in hardware to increase performance, while retaining the flexibility of application software. The purpose of this paper is to meet the demand of a suitable design flow for a reconfigurable computing system using Hybrids architecture. The two main types of programmable logic devices, field-programmable gate arrays (FPGA) based on LUTs technology and complex programmable logic device (CPLD) based on PLAs technology. They are both widely used and each contributing particular strengths in the area of reconfigurable system design. In this paper, we try to propose computer-aided design (CAD) optimization technique for Hybrid Reconfigurable Computing Architecture (HRCA), which combines FPGAs and CPLDs. The basis of the HRCA is that some parts of digital circuits are well-suited for execution with LUTs, but other parts help more from the PLAs structures. The new architecture HRCA offers significant savings in total logic area comparison with an architecture containing only LUTs. It also offers some improvements in speed performance. This paper focuses on suitable optimization techniques and design flow that will cover all major steps in system design which includes: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behaviour-level synthesis.