CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
Reseach Article

Unified System Level Fault Modeling and Fault Propagation

by Hara Gopal Mani Pakala, Dr. KVSVN Raju, Dr. Ibrahim Khan
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 23 - Number 8
Year of Publication: 2011
Authors: Hara Gopal Mani Pakala, Dr. KVSVN Raju, Dr. Ibrahim Khan
10.5120/2904-3813

Hara Gopal Mani Pakala, Dr. KVSVN Raju, Dr. Ibrahim Khan . Unified System Level Fault Modeling and Fault Propagation. International Journal of Computer Applications. 23, 8 ( June 2011), 34-41. DOI=10.5120/2904-3813

@article{ 10.5120/2904-3813,
author = { Hara Gopal Mani Pakala, Dr. KVSVN Raju, Dr. Ibrahim Khan },
title = { Unified System Level Fault Modeling and Fault Propagation },
journal = { International Journal of Computer Applications },
issue_date = { June 2011 },
volume = { 23 },
number = { 8 },
month = { June },
year = { 2011 },
issn = { 0975-8887 },
pages = { 34-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume23/number8/2904-3813/ },
doi = { 10.5120/2904-3813 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:09:38.470761+05:30
%A Hara Gopal Mani Pakala
%A Dr. KVSVN Raju
%A Dr. Ibrahim Khan
%T Unified System Level Fault Modeling and Fault Propagation
%J International Journal of Computer Applications
%@ 0975-8887
%V 23
%N 8
%P 34-41
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Fault modeling is an important step towards both understanding and validating the implemented system. The focus of the paper is to present a unified system fault modelling framework, including input related faults model based on system theory. The complex embedded system (CES) is modelled using sequence of communicating FSM (SCFSM) and the system faults are represented by two components of system fault vector - system behaviour fault vector and system communication fault vector. These two system fault vector components are related and are components of the “change parameter vector Θ”, a general system level fault model based on Dynamic system theory. Input related faults are defined and their contribution is discussed. Faults propagation in mixed hardware software communication architecture is discussed, with the help of protocol example.

References
  1. Tom Henzinger, Joseph Sifakis. "The embedded systems design challenge". Proceedings of the 14th International Symposium on Formal Methods (FM), Lecture Notes in Computer Science, Springer, August, 2006.
  2. Bernhard K. Aichernig, Martin Weiglhofer, Franz Wotawa “Improving Fault-based Conformance Testing”, Electronic Notes in Theoretical Computer Science 220 (2008) 63–77.
  3. Vadim Okun a,b Paul E. Black a Yaacov Yesha, Comparison of Fault Classes in Specification-Based Testing , Preprint submitted to Elsevier Science 2 April 2004
  4. Leonardo Mariani, “A Fault Taxonomy for Component-based Software” Electronic Notes in Theoretical Computer Science 82 No. 6 (2003).
  5. M. Basseville and I. Nikiforov (1993). Detection of Abrupt Changes: Theory and Applications. Prentice Hall, N.J.
  6. A Guerrouat, and Harald Richter, Adaptation of State/Transition-Based Methods for Embedded System Testing” Proceedings Of World Academy Of Science, Engineering And Technology Volume 10 December 2005 Issn 1307-6884
  7. Qiushuang Zhang and Ian G. Harris, “A Validation Fault Model for Timing-Induced Functional Errors”, International Test Conference 2001 (ITC'01) Baltimore, Maryland, October 30-November 01.
  8. Boris Beizer, “ Software Testing Techniques”, Second Edition The Coriolis Group ISBN: 1850328803 Date: 06/01/90
  9. R. R. Lutz. Analyzing software requirements errors in safety-critical, embedded systems. In IEEE International Symposium on Requirements Engineering, pages 126–133, San Diego, CA, 1993. IEEE Computer Society Press.
  10. T. L. Bennett and Paul Wennberg, “Eliminating Embedded Software Defects Prior to Integration Test”, Triakis Corporation ; VSILTriakis2005Article-c
  11. Man F. Lau, Yuen T. Yu, “An Extended Fault Class Hierarchy for Specification-Based Testing” ACM Transactions on Software Engineering and Methodology, Vol. 14, No. 3, July 2005, Pages 247–276.
  12. P. Prema, and B. Ramadoss, “A New Type of Integration Error and its Influence on Integration Testing Techniques”, World Academy of Science, Engineering and Technology 42 2008.
  13. Abramovici, M., Breuer, M., and Friedman, A. D., Digital Systems Testing and Testable Design. IEEE, 1993
  14. Ian G. Harris, “Fault Models and Test Generation for Hardware-Software Co-validation” IEEE Design & Test Volume 20 , Issue 04 (July 2003) Pages: 40 - 47
  15. Goradia, T., “Dynamic impact analysis: a cost-effective technique to enforce error-propagation”, Proc. Int. Symp. On Software Testing and Analysis (ISSTA ’93), Cambridge, MA, U.S.A., ACM Press, pp. 171-181 (June 1993).
  16. Petrenko, A., Yevtushenko, N., Bochmann, G., and Dssouli, R. (1996). Testing in context: Framework and test derivation. Computer Communications, 19: 125-140.
  17. Hara Gopal Mani Pakala, K. V. S. V. N. Raju and Ibrahim Khan, “ Integration Testing of Multiple Embedded Processing Components”, Springer Advanced Computing, Communications in Computer and Information Science, 2011, Volume 133, Part 2, 200-209.
  18. J. Schmaltz and D. Borrione, “Validation of a Parameterized Bus Architecture Model,” Proc. TIMA-VDS, 2003.
  19. J. A. Rowson and A. Sangiovanni-Vincentelli, “Interface-based design”, in Design Automation Conference, pp. 178–183, June 1997.
  20. D. Panigrahi, C. N. Taylor, and S. Dey, “Interface based hardware/software validation of a system-on-chip”, in High Level Design Validation and Test Workshop, pp. 53–58, 2000.
  21. Hara Gopal Mani Pakala, Dr. Raju KVSVN and Dr. Ibrahim Khan, “Sensors Integration in Embedded Systems”, International Conference on Power, Control and Embedded Systems (ICPCES 2010) Nov 29, 2010 - Dec 1, 2010 Allahabad, India
  22. Victor Vui-Kiat Chong, “Heuristics for Mitigating Mode Confusion in Digital Cameras” A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Computer Science, University of Victoria, 2006
  23. Jane Huffman Hayes, Jeff Offutt, “Input Validation Analysis and Testing” pp1-29, Empirical Software Engineering ©2005 Kluwer Academic Publishers.
  24. Hermann Kopetz, "The Complexity Challenge in Embedded System Design," isorc, pp.3-12, 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing (ISORC), 2008.
  25. John Sanguinetti, Abstraction Levels and Hardware Design, EDA Design Line (07/17/07).
  26. W. Ecker, V. Esen, T. Steininger, and M. Velten. HW/SW interface - implementation and modeling. In W. Ecker, W. M¨uller, and R. D¨omer, editors, Hardware-dependent Software - Principlesand Practice. Springer, 2008
  27. Andreas Gerstlauer, Daniel D. Gajski, "System-Level Abstraction Semantics," CECS, UC Irvine, Technical Report CECS-TR-02-17, July 2002.
Index Terms

Computer Science
Information Sciences

Keywords

System level Faults model Fault propagation system fault vector components behaviour fault vector communication channel fault vector embedded system Sequence of CFSM