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Reseach Article

A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub Micron CMOS Technology

by Neeraj Kr. Shukla, R. K. Singh, Manisha Pattanaik
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 23 - Number 7
Year of Publication: 2011
Authors: Neeraj Kr. Shukla, R. K. Singh, Manisha Pattanaik
10.5120/2899-3796

Neeraj Kr. Shukla, R. K. Singh, Manisha Pattanaik . A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub Micron CMOS Technology. International Journal of Computer Applications. 23, 7 ( June 2011), 23-28. DOI=10.5120/2899-3796

@article{ 10.5120/2899-3796,
author = { Neeraj Kr. Shukla, R. K. Singh, Manisha Pattanaik },
title = { A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub Micron CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { June 2011 },
volume = { 23 },
number = { 7 },
month = { June },
year = { 2011 },
issn = { 0975-8887 },
pages = { 23-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume23/number7/2899-3796/ },
doi = { 10.5120/2899-3796 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:09:32.534328+05:30
%A Neeraj Kr. Shukla
%A R. K. Singh
%A Manisha Pattanaik
%T A Novel Approach to Reduce the Gate and Sub-threshold Leakage in a Conventional SRAM Bit-Cell Structure at Deep-Sub Micron CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 23
%N 7
%P 23-28
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the age of scaled silicon technology to improve the functional efficiency of a CMOS design, the device geometry and device parameters are constantly scaled. The major factors of the power consumption due to continuous reduction of the oxide thickness (tOX) is the gate leakage current in both the active and standby mode of the device and other is due to scaled supply voltage, the sub-threshold leakage current. This work proposes a novel approach called as the P3 SRAM Bit-Cell Scheme for the reduction of the active and standby leakage power through the gate and sub-threshold leakage reduction in the active and standby mode of the memory operation. As the gated transistor is of minimum feature size, so the area penalty is minimum in terms of a large memory and can be compromised. To the best of my knowledge, pMOS Gated-Ground and full-supply voltage body bias for pMOS transistor along with the PP SRAM bit-cell structure is used for the first time in the memory bit-cell design to reduce the power in 45nm CMOS technology at VDD = 0.7V and 0.8V. In comparison with the Conventional and PP SRAM Bit-cells, the active power is achieved for Write Data ‘0’ as 89.21% , 94.38%, and for Write Data ‘1’ as 89.23%, 94.45%, respectively at VDD = 0.7V. When the VDD = 0.8V, the active power is achieved for Write Data ‘0’ as 9.15%, 93.63%, and for Write Data ‘1’ as 91.68%, 93.59%, respectively.

References
  1. Neeraj Kr. Shukla, R.K. Singh, and Manisha Pattanaik, “Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications”, International Journal of Advanced Computer Science and Applications (IJACSA), USA, Vol.2, Issue 5, May, 2011, pp. 43-49.
  2. International Technology Roadmap for Semiconductors. Online-Available at http://www.publicitrs.net
  3. K. M. Kao, et. al., “BSIM4 Gate Leakage Model Including Source-Drain Partition,” in Proc. Int. Electron Devices Meeting, Dec. 2000, pp. 815–818.
  4. Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang,B. Zheng, and Mark Bohr, “SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction” IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, APRIL 2005, pp. 895-901.
  5. B.S. Deepaksubramanyan and Adrian Nu˜nez, “Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits”, Proceedings of the 13th NASA VLSI Symposium, Post Falls, IDAHO, USA, June 5-6, 2007, pp 1-8.
  6. Neeraj Kr. Shukla, Shilpi Birla, R.K. Singh, and Manisha Pattanaik, “Speed and Leakage Power Trade-off in Various SRAM Circuits”, International Journal of Computer and Electrical Engineering (IJCEE), Singapore, Vol.3, No.2, Apr. 2011, pp. 244-249.
  7. Sung-Mo (Steve) Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Third Edition Tata McGraw-Hill Edition, New Delhi, India.
  8. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. New York: Cambridge Univ. Press, 1998, ch. 2, pp. 94–95.
  9. K. Cao,W.-C Lee,W. Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source drain partition,” in Tech. Dig. Int. Electron Devices Meeting, 2000, pp. 815–818.
  10. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, G. Sai-Halasz, R.Viswanathan, and et al., “CMOS scaling into nanometer regime”, Proc. of the IEEE, vol. 85, Apr. 1997, pp. 486–504.
  11. G. Razavipour, A. Afzali-Kusha, and M. Pedram, “Design and Analysis of Two Low-Power SRAM Cell Structures”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, Oct. 2009, pp. 1551-1555.
  12. Behnam Amelifard, Farzan Fallah, and Massoud Pedram, “Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment”, Proceeding of Design, Automation and Test in Europe, Munich, 2006. Date: 6-10 March 2006, pp. 1-6.
  13. K. Nil, et.al., “ A Low-Power SRAM using Auto-Backgate-Controlled MT-CMOS”, Proceedings of the International Symposium on Low-Power Electronics and Design, Aug. 1998, pp. 293-98.
Index Terms

Computer Science
Information Sciences

Keywords

Deep-Sub Micron Gate Leakage Sub-threshold Leakage PP-SRAM Stacking Effect