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Reseach Article

Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption

by Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 22 - Number 7
Year of Publication: 2011
Authors: Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V
10.5120/2599-3613

Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V . Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption. International Journal of Computer Applications. 22, 7 ( May 2011), 1-7. DOI=10.5120/2599-3613

@article{ 10.5120/2599-3613,
author = { Pavan.T.K, Jagannadha Naidu.K, Nagaraju.V },
title = { Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption },
journal = { International Journal of Computer Applications },
issue_date = { May 2011 },
volume = { 22 },
number = { 7 },
month = { May },
year = { 2011 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume22/number7/2599-3613/ },
doi = { 10.5120/2599-3613 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:08:44.852737+05:30
%A Pavan.T.K
%A Jagannadha Naidu.K
%A Nagaraju.V
%T Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption
%J International Journal of Computer Applications
%@ 0975-8887
%V 22
%N 7
%P 1-7
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.

References
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Index Terms

Computer Science
Information Sciences

Keywords

CMOS leakage current supply voltage control threshold voltage control switching current