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Reseach Article

Modified PSO based Adaptive IIR Filter Design for System Identification on FPGA

by Lipika Gupta, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 22 - Number 5
Year of Publication: 2011
Authors: Lipika Gupta, Rajesh Mehra
10.5120/2583-3569

Lipika Gupta, Rajesh Mehra . Modified PSO based Adaptive IIR Filter Design for System Identification on FPGA. International Journal of Computer Applications. 22, 5 ( May 2011), 1-7. DOI=10.5120/2583-3569

@article{ 10.5120/2583-3569,
author = { Lipika Gupta, Rajesh Mehra },
title = { Modified PSO based Adaptive IIR Filter Design for System Identification on FPGA },
journal = { International Journal of Computer Applications },
issue_date = { May 2011 },
volume = { 22 },
number = { 5 },
month = { May },
year = { 2011 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume22/number5/2583-3569/ },
doi = { 10.5120/2583-3569 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:08:35.496072+05:30
%A Lipika Gupta
%A Rajesh Mehra
%T Modified PSO based Adaptive IIR Filter Design for System Identification on FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 22
%N 5
%P 1-7
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper focuses on the implementation of Adaptive Infinite Impulse response (IIR) filter on an FPGA using Modified Particle Swarm Optimization (PSO) Algorithm. The proposed Filter is capable of finding the global optimum solution for system identification problem in less number of iterations. The modified PSO algorithm has been developed and simulated using MATLAB. The result shows the enhanced speed of purposed design in terms of number of iterations it takes to identify the unknown system. The same algorithm has also been realized on various Xilinx FPGA devices and performances have also been analyzed. The area utilization by the proposed design on different FPGA devices has been compared. The results show that proposed filter is consuming very less area in terms of LUTs and Slices to provide enhanced area efficiency.

References
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Index Terms

Computer Science
Information Sciences

Keywords

FPGA IIR Filter LUTS MATLAB PSO