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High Speed CT Image Reconstruction using FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 22 - Number 4 |
| Year of Publication: 2011 |
| Authors: Payal Aggarwal, Rajesh Mehra |
10.5120/2574-3550
|
Payal Aggarwal, Rajesh Mehra . High Speed CT Image Reconstruction using FPGA. International Journal of Computer Applications. 22, 4 ( May 2011), 7-10. DOI=10.5120/2574-3550
Abstract
Tomographic image reconstruction methods suffer from time consuming back projection steps due to large computation. This drawback can be minimized by its hardware implementation on FPGA to provide high speed image reconstruction. This paper presents the reconfigurable design of filtered backprojection (FBP) for parallel beam CT. The proposed design has been implemented by efficiently utilizing the embedded multipliers and LUTs of target FPGA device. The design has been developed using MATLAB and synthesized with Xilinx synthesis tool (XST) and implemented on Virtex 2 Pro based xc2vp30-7ff896 target device. The results show that the proposed design can operate at a maximum frequency of 144.744 MHz to provide high speed solution for image processing applications.
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