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Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 22 - Number 3 |
| Year of Publication: 2011 |
| Authors: Dinesh Sharma, Rajesh Mehra |
10.5120/2565-3526
|
Dinesh Sharma, Rajesh Mehra . Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology. International Journal of Computer Applications. 22, 3 ( May 2011), 13-18. DOI=10.5120/2565-3526
Abstract
This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold voltage (Vth) are scaled for low voltage applications in deep submicron (DSM) region. The proposed buffer has been designed and simulated using Tanner SPICE tool in 70 nm VLSI technology node. The results show that modified taper buffer design provides 15% reduction in power dissipation at same value of propagation delay when compared with conventional design.
References
- W. J. Dally, “Interconnect-limited VLSI architecture,” in Proceeding of IEEE International Conference on Interconnect Technology, pp.15–17, 1999.
- J. D. Meindl, ‘‘Beyond Moore’s law: The interconnect era,’’ Computer Science and Engineering. pp. 20-24, 2003.
- Ahmed Shebaita and Yehea Ismail, “Multiple threshold voltage design scheme for CMOS Tapered Buffers” IEEE Transactions on circuits and Systems-II, Vol. 55, Page(s): 21 - 25 , January 2008.
- Ahmed Shebaita and Yehea Ismail “Lower power, lower delay Design scheme for CMOS Tapered Buffers” , Design & Test Workshop (IDT), Page(s): 1 - 5 , 2009
- N. C. Li, G. L. Haviland and A. A. Tuszynski, “CMOS tapered buffer,” IEEE I.S.SC., vol. 25, no. 4, pp. 1005-1008, 1990.
- B. S. Cherkauer and E. G. Friedman, “A unified design methodology for CMOS tapered buffers,” IEEE Transactions on VLSI Syst., vol. 3, no. 1, 1995.
- K. Roy, S. Mukhopadhyay, and H. Mahmoodi “ Leakage current mechanism and leakage reduction techniques in DSM CMOS circuits”, IEEE Proceeding., vol 91 No. 2, Feb. 2003
- HeungJun Jeon, Yong-Bin Kim, “Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI System” IEEE transactions on instrumentation and measurement, VOL. 59, NO. 5, Page(s): 1127 – 1133, MAY 2010
- Bisdounis, L. “Short-circuit energy dissipation model for sub-100nm CMOS buffers”17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Page(s): 615 - 618, 2010.
- Kyung Ki Kim; Yong-Bin Kim; Minsu Choi; Park, N. “Leakage minimization technique for nano scale CMOS VLSI” Design &Test of Computers, IEEE Volume: 24 , Issue: 4 , Page(s): 322 – 330, 2007.
- H. J. M. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp.468-473, Aug. 1984.
- C. yoo, “A CMOS Buffer without Short-Circuit Power Consumption,” IEEE Trans. Circuit Syst. II, vol. 47, No. 9, pp. 935-937, 2000.
- Tadahiro Kuroda “Optimization and control of VDD and VTH for low-power, high-speed CMOS design”, in Proceedings of IEEE/ACM international conference on Computer-aided design San Jose, California, Page(s): 28 - 34 ,2002 .
- Koichi Nose and Takayasu Sakurai “Optimization of VDD and VTH for low-power and high-speed applications”, Proceedings of Asia and South Pacific Design Automation Conference Yokohama, Japan ,Page(s): 469 - 474 , 2000 .
- Haghdad, K.; Anis, M “Design specific optimization considering supply and threshold voltage variations” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 27 , Issue: 10 , Page(s): 1891 - 1901, 2008.
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