We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
Reseach Article

Design and VLSI Implementation of a High Throughput Turbo Decoder

by Aso.M.Raymond, Dr.C.Arun
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 22 - Number 3
Year of Publication: 2011
Authors: Aso.M.Raymond, Dr.C.Arun
10.5120/2562-3520

Aso.M.Raymond, Dr.C.Arun . Design and VLSI Implementation of a High Throughput Turbo Decoder. International Journal of Computer Applications. 22, 3 ( May 2011), 33-37. DOI=10.5120/2562-3520

@article{ 10.5120/2562-3520,
author = { Aso.M.Raymond, Dr.C.Arun },
title = { Design and VLSI Implementation of a High Throughput Turbo Decoder },
journal = { International Journal of Computer Applications },
issue_date = { May 2011 },
volume = { 22 },
number = { 3 },
month = { May },
year = { 2011 },
issn = { 0975-8887 },
pages = { 33-37 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume22/number3/2562-3520/ },
doi = { 10.5120/2562-3520 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:08:28.874409+05:30
%A Aso.M.Raymond
%A Dr.C.Arun
%T Design and VLSI Implementation of a High Throughput Turbo Decoder
%J International Journal of Computer Applications
%@ 0975-8887
%V 22
%N 3
%P 33-37
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Turbo codes are one of the most efficient error correcting code which approaches the Shannon limit. However the major drawback of turbo codes is its high latency due to its iterative decoding process. The high throughput in turbo decoder can be achieved by parallelizing several Soft Input Soft Output(SISO) units together. In this way, multiple SISO decoders work on the same data frame at the same time. When more number of SISO decoders is connected parallel, the turbo interleaver creates a bottleneck in the system due to the contentions it introduces in accesses to memory. This delays the decoding process. In this paper, an advanced parallel interleaver called Quadratic Permutation Polynomial (QPP)interleaver is used which resolves the memory collisions introduced by parallel SISO decoders. The required area for the chip can be reduced by the help of efficient utilization of the SISO decoders. A method called Next Iteration Initialization is also used in order to reduce latency produced by a turbo decoder. The proposed Turbo decoder is expected to provide a throughput above 100Mbps.

References
  1. C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes,” in Proc. 1993 InternationalConference on Communications (ICC ’93), Geneva, Switzerland, May 1993, pp. 1064–1070.
  2. Claude Berrou, Alain Glavieux and Punya Thitimajshima, “Near shannon limit error – correcting Coding and decoding : turbo-codes” IEEE Transactions on Communications, 44:1261 – 1271,Oct.1996.
  3. Third Generation Partnership Project, “3GPP home page” www.3gpp.org.
  4. Vogt.J and Finger.A, “Improving the max-log-MAP turboDecoder,” Electron. Lett., vol. 36, no.23, pp.1937-1939, Nov 2000.
  5. K. Loo, T. Alukaidey, and S. Jimaa, “High performance parallelised 3GPP turbo decoder," in IEEE Personal Mobile Communications Conference, April 2003, pp. 337-342.
  6. A.J. Viterbi. An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes. IEEE J.Sel. Areas Commun., vol.16:pp.260–264, Feb.1998.
  7. R. Dobkin, M.Peleg, and R.Ginosar. Parallel interleaver design and vlsi architecture for low-latency map turbo decoders. IEEE Trans.VLSI Syst., 13(4):427–438, 2005.
  8. Y.Sun, Y.Zhu, M.Goel, and J.R.Cavallaro. Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards. In IEEE International Conference on Application-Specific Systems, Architectures and Processors(ASAP), pages 209–214, July2008.
  9. J. Sun and O.Y.Takeshita. Interleavers for turbo codes using permutation polynomials over integer rings. IEEE Trans.Inform.Theory, vol.51:101– 119, Jan.2005.
  10. O.Y.Takeshita.Onmaximumcontention-freeinterleaversand permutation polynomialsoverintegerrings. IEEE Tran .Inform.Theory, vol.52:1249–1253,Mar.2006.
Index Terms

Computer Science
Information Sciences

Keywords

Parallel processing SISO decoders Next Iteration Initialization QPP interleaver