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Simulation and Verification of Self Test 16-Bit Processor
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 20 - Number 1 |
| Year of Publication: 2011 |
| Authors: Manoranjan Pradhan |
10.5120/2394-3180
|
Manoranjan Pradhan . Simulation and Verification of Self Test 16-Bit Processor. International Journal of Computer Applications. 20, 1 ( April 2011), 42-45. DOI=10.5120/2394-3180
Abstract
This paper presents the design and verification of 16 bit processor. The Booth multiplier and restoring division are integrated in to the ALU of the proposed processor. The processor is described in structural level to verify the general understanding of the system. The processor has 16-bit instruction based on three different format R-format, I-format and J-format. The control unit generates all the control signals needed to control the coordination among the entire component of the processor. All the modules in the design are coded in VHDL (very high speed integrated circuit hardware description language) to ease the description, verification, simulation and hardware implementation. The design entry, synthesis, and simulation of processor are done by using Xilinx ISE 10.1 software and implemented on XC2S200-6pq208 Spartan-II FPGA device.
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