An important step in the automation of electronic design is the assignment of the physical components on the target semiconductor die. The major aim of floorplanning is to distribute the modules of a circuit onto a chip to optimize its area, wire length and timing. As the density of very large scale integrated (VLSI) circuits enhance, the need for faster floorplanning algorithms also grows. The goal of this work is to produce a fast method for developing wire-optimized floorplan. This uses trapezoidal algorithm for floorplanning. The generalized trapezoidal algorithm combines the major physical design steps in one algorithm. By the use of connectivity grouping, simple geometry, and a constrained brute-force approach, trapezoidal algorithm achieves lesser wire estimate than simulated annealing (SA) in orders of magnitude less time. It derives its advantages from the two important concepts of mathematics ie constraint brute-force-approach and divide-and-conquer approach. This generalised trapezoidal algorithm considers the softblocks.In addition; this algorithm implemented the multilevel partitioning with weighted aggregation scheme (WAG) scheme. The speed of this algorithm allows the designers to get a quick feedback about the design of larger circuits.

Floorplanning Trapezoidal algorithm multilevel partitioning weighted aggregation scheme