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FPGA Implementation of RSA Encryption System

by Sushanta Kumar Sahu, Manoranjan Pradhan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 19 - Number 9
Year of Publication: 2011
Authors: Sushanta Kumar Sahu, Manoranjan Pradhan
10.5120/2391-3173

Sushanta Kumar Sahu, Manoranjan Pradhan . FPGA Implementation of RSA Encryption System. International Journal of Computer Applications. 19, 9 ( April 2011), 10-12. DOI=10.5120/2391-3173

@article{ 10.5120/2391-3173,
author = { Sushanta Kumar Sahu, Manoranjan Pradhan },
title = { FPGA Implementation of RSA Encryption System },
journal = { International Journal of Computer Applications },
issue_date = { April 2011 },
volume = { 19 },
number = { 9 },
month = { April },
year = { 2011 },
issn = { 0975-8887 },
pages = { 10-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume19/number9/2391-3173/ },
doi = { 10.5120/2391-3173 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:06:30.900690+05:30
%A Sushanta Kumar Sahu
%A Manoranjan Pradhan
%T FPGA Implementation of RSA Encryption System
%J International Journal of Computer Applications
%@ 0975-8887
%V 19
%N 9
%P 10-12
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the architecture and modeling of RSA public key encryption/decryption systems. It supports multiple key sizes like 128 bits, 256 bits, 512 bits. Therefore it can easily be fit into the different systems requiring different levels of security. In this paper simple shift and add algorithm is used to implement the blocks. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block is coded with Very High Speed Integrated Circuit Hardware Description Language. The VHDL code is synthesized and simulated using Xilinx-ISE 10.1. It is verified that this architecture support multiple key of 128bits, 256bits, and 512 bits

References
  1. SCHNEIER, B., 1996. Applied Cryptography: Protocols, Algorithms, and Source Code in C, John Wiley & Sons.
  2. Deng Y., Mao Z., and Ye Y.,. 1998. Implementation of RSA Crypto-Processor Based on Montgomery Algorithm.
  3. Zhang. C.N, Xu. Y and Wu. C., 1997. A Bit-Serial Systolic Algorithm and VLSI Implementation for RSA.
  4. Hinek. M., 2010. Cryptanalysis of RSA and Its Variants.
  5. Rivest, R., Shamir, A., and Adleman, L, 1978. A Method for Obtaining Digital Signatures and Public Key Cryptosystems. Communications of the ACM.
  6. Stallings W.2003, Cryptography and Network Security: Principles and Practices.
  7. Burnett S. and Paine S, 2001. RSA Security’s Official Guide to Cryptography. McGraw-Hill.
  8. Ashenden P. and Lewis J, 2006. The Designer’s Guide to VHDL. Morgan Kaufmann Publishers.
  9. Hwang E. Digital Logic and Microprocessor Design with VHDL.
  10. Nedjah.N and Mourelle L.2002.Two Hardware Implementation for the Montgomery Modular Multiplication: Sequential versus Parallel. IEEE.
Index Terms

Computer Science
Information Sciences

Keywords

RSA VHDL FPGA modular multiplication.

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