| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 187 - Number 144 |
| Year of Publication: 2026 |
| Authors: K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S. |
10.5120/ijca2bef88369267
|
K. Ezhilarasan, Kaveri S., K. Bhavya Sree, Shreyas M., Vidyashree K.S. . Optimized 4:2 Compressor based Approximate Multiplier for Low Power Digital Signal Processing. International Journal of Computer Applications. 187, 144 ( Sep 2026), 7-18. DOI=10.5120/ijca2bef88369267
In many digital signal processing systems, multiplication is the workhorse and also the biggest drain on power, area, and latency. This paper introduces an elegant compressor an enhanced multiplier built around approximate 4:2 compressors that trims energy and hardware cost while preserving the fidelity that matters. The design uses a hybrid compression strategy; the most significant bits are handled by exact 4:2 compressors to protect numerical accuracy where it counts, while the least significant bits are handled by lightweight approximate 4:2 compressors. By selectivity relaxing correctness only where the impact on the overall result is small, the architecture dramatically reduces switching activity, shortens critical – path delay, and shrink resource usage. Partial products are aggregated in a structured compression tree and finished off with a fast final adder to produce the product. To quantify trade-offs, the design is evaluated on power, propagation delay, area, and accuracy metrics (Mean Error Distance and Error Rate). Results show notable improvements in power–delay product and area efficiency compared with exact multipliers, while introducing only modest, generally acceptable errors. The result is a compelling multiplier option for DSP contexts that can tolerate slight inaccuracies in exchange for lower power and smaller silicon footprint.