CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder

by V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N.
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 184 - Number 50
Year of Publication: 2023
Authors: V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N.
10.5120/ijca2023922620

V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N. . Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder. International Journal of Computer Applications. 184, 50 ( Mar 2023), 15-21. DOI=10.5120/ijca2023922620

@article{ 10.5120/ijca2023922620,
author = { V. Thamizharasan, Gokulapriya M., Madhubala M., Divya T., Ramya N. },
title = { Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder },
journal = { International Journal of Computer Applications },
issue_date = { Mar 2023 },
volume = { 184 },
number = { 50 },
month = { Mar },
year = { 2023 },
issn = { 0975-8887 },
pages = { 15-21 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume184/number50/32643-2023922620/ },
doi = { 10.5120/ijca2023922620 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:24:29.624867+05:30
%A V. Thamizharasan
%A Gokulapriya M.
%A Madhubala M.
%A Divya T.
%A Ramya N.
%T Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 184
%N 50
%P 15-21
%D 2023
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Nowadays a mobile computing and multimedia applications are need for high-performance, reduced size and low-power. One of the most widely used operations in DSP is Multiplication. Different types of multipliers are available in digital. In these multipliers the Vedic multiplier is the most optimized multiplier used in signal processing module. In the existing method Vedic multiplier is designed with conventional adders, which having higher area utilization, lower speed, and power consumption. The proposed design presents a proficient Vedic multiplier architecture for high-performance applications. Vedic multiplier architecture is consisting of adders. The proposed scheme is to changing the architecture of multiplier by memory-oriented adder cell which specifically doing add the partial product of the multiplier in memory-based approach. Which is a high speed and low area adder. This Multiplier is functionally verified/simulated using Modelsim software and implemented to Spartan3E FPGA kit using Xilinx12.1 software. Also analyze the performance parameter like area, speed and power will be compared to conventional multiplier & adder architectures.

References
  1. Chyn Wey-I, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng., “An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term,” IMECS, Volume II ,pp. 1091-1094.Mar.2012.
  2. Poornima M, Shivaraj Kumar Patil, Shivukumar, Shridhar K P,Sanjay H “Implementation of Multiplier using Vedic Algorithm,” Int. J. of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-2, Issue-6. May 2013.
  3. Premananda B.S., Samarth S. Pai, Shashank B., Shashank S. Bhat “Design and Implementation of 8-Bit Vedic Multiplier,” Int. J. of Advanced Research in Electrical, Electronics and Instrumentation Engineering,Volume. 2, Issue 12, Dec.2013.
  4. Jasbirkaur, lalitsood “Comparison between Various Types of Adder Topologies,” IJCST Volume. 6, Issue 1. Mar.2015
  5. J.Eric Clapten, E. Konguvel, M. Thangamani, “VLSI Implementation of Low Power Area Efficient Fat Carry Select Adder,” Int. J. of Communications, Volume 115-No.6 Mar.2015
  6. H. Dorosti, A. Teymouri, S. M. Fakhraie and M. E. Salehi, "Ultralow-Energy Variation-Aware Design: Adder Architecture Study," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 3, pp. 1165-1168, March 2016.
  7. D. K. Patel, R. Chouksey and M. Saxena, "Design of fast FIR filter using compressor and Carry Select Adder," 3rd International Conference on Signal Processing and Integrated Networks (SPIN), pp. 460-465, 2016.
  8. S. Srikanth, I. T. Banu, G. V. Priya and G. Usha, "Low power array multiplier using modified full adder,” IEEE International Conference on Engineering and Technology (ICETECH), 2016, pp. 1041-1044,2016.
  9. Rajeswar Reddy B, Lakshmi Prasad E and A. R. Reddy, "Multi precision arithmetic adders,” International Conference on Computer Communication and Informatics (ICCCI), 2016, pp. 1-6, 2016.
  10. V .Thamizharasan and V .Parthipan, “An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier,” Int. J. of Computer applications, Vol. 54, no.14, pp.1-6, Sep.2012.
  11. V.Thamizharasan and N.Kasthuri, “High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation," in IETE Journal of Research, pp. 1-9, Apr.2021.
  12. V.Thamizharasan and N.Kasthuri, “Design of Proficient Two operand adder using Hybrid Carry Select adder with FPGA implementation, pp. 1-14, May.2022.
  13. V.Thamizharasan and N.Kasthuri, “FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier, pp. 1-21, July.2022.
Index Terms

Computer Science
Information Sciences

Keywords

DSP Vedic multiplier Spartan 3E FPGA Xilinx12.1

Powered by PhDFocusTM