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High Speed Compressor based Adder using XOR-XNOR Gate: A Study
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 184 - Number 23 |
| Year of Publication: 2022 |
| Authors: Monika Singh, Prashant Chaturvedi |
10.5120/ijca2022922272
|
Monika Singh, Prashant Chaturvedi . High Speed Compressor based Adder using XOR-XNOR Gate: A Study. International Journal of Computer Applications. 184, 23 ( Jul 2022), 12-15. DOI=10.5120/ijca2022922272
Abstract
Multiplier is an essential block of a computing device. Multipliers are commonly used for signal and image processing applications where multipliers are used to perform various tasks like convolution, correlation and filtering. Multipliers are not only a high delay component but also dissipate high amount of power. It is necessary to increase the speed of multipliers as the demand of high speed processors is increasing. More over, multipliers is an integral part of any processor and are utilized by the processors to complete signal processing tasks. Optimizing performance of multipliers provides bet ter results in digital signal processors. In multiplier, reduction of partial products takes more time and consumes high power. A huge number of adders are used to perform the partial product reduction operation. Optimizing the partial products reduction is a challenging task for researchers. Compressors take more inputs at a time and are able to process partial products in a faster way compared to conventional adders. Use of compressors in the partial product reduction helps to minimize the delay but not power consumption.
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