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Reseach Article

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

by Hadi Jahanirad
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 180 - Number 43
Year of Publication: 2018
Authors: Hadi Jahanirad
10.5120/ijca2018917136

Hadi Jahanirad . Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA. International Journal of Computer Applications. 180, 43 ( May 2018), 42-49. DOI=10.5120/ijca2018917136

@article{ 10.5120/ijca2018917136,
author = { Hadi Jahanirad },
title = { Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA },
journal = { International Journal of Computer Applications },
issue_date = { May 2018 },
volume = { 180 },
number = { 43 },
month = { May },
year = { 2018 },
issn = { 0975-8887 },
pages = { 42-49 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume180/number43/29422-2018917136/ },
doi = { 10.5120/ijca2018917136 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:03:32.597199+05:30
%A Hadi Jahanirad
%T Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 180
%N 43
%P 42-49
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a co-evolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

References
  1. J. Hogan, R. Weber and B. LaMeres, “Reliability Analysis of Field-Programmable Gate-Array-Based Space Computer Architectures,” J. Aerospace info. Syst., 2017, pp. 121–133.
  2. A. Sari, G. Agiakatsikas andM. Psarakis, “A soft error vulnerability analysis framework for Xilinx FPGAs,” in Proc. ACM/SIGDA int.symp. on Field-programmable gate arrays, 2014, pp. 234–240.
  3. P. McNelles, L. Lu, “Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology,” Nuclear Engineering and Technology, vol. 48, no. 5, Oct. 2016, pp. 1192-1205.
  4. K. A. Hoque, O. A. Mohammad, and Y. Savaria, “Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications,” Journal of Applied Logic, vol. 25, no. 1, Dec. 2017, pp. 47–68.
  5. H.Ebrahimi, M. Saheb-Zamani, H.R. Zarandi, "Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes", Microelectronics Journal, vol. 42, no. 1, January, 2011, pp. 12-20.
  6. H. Asadi, M.B. Tahoori, B. Mullins, D. Kaeli, K. Granlund, “Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems”, IEEE Transaction on Nuclear Science, vol. 54, no. 6, 2007, pp 2714–2726.
  7. J. Han, H. Chen, J. Liang, P. Zhu, Z. Yang, and F. Lombardi, “A stochastic computational approach for accurate and efficient reliability evaluation,” IEEE Trans. Comp. vol. 63, no. 6, Jun. 2014.
  8. S. Bodapati, and K. Sridharan, “A transistor-level probabilisticapproach for reliability analysis of arithmetic circuits withapplication to emerging technologies,” IEEE Trans Reliability, vol. 66, no. 2, June 2017.
  9. C. Chen, and R Xiao, “A fast model for analysis and improvementof gate-level circuit reliability,” Integration, the VLSI Jour. vol. 50, pp. 107-115, Jun. 2015.
  10. Bhaduri D, Shukla S. NANOPRISM: “a tool for evaluating granularity versus reliability trade-offs in nano architectures”, Proceedings of the 14th ACM Great Lakes symposium on VLSI, 2004. p. 109–12.
  11. Norman G, Parker D, Kwiatkowska M, Shukla S. “Evaluating the reliability of NAND multiplexing with PRISM”. IEEE Trans Comput Aided DesIntegr Circuits Syst, vol 24, no. 10, pp1629–37, 2005
  12. Clarke E, Fujita M, McGeer P, Yang J, Zhao X, “Multiterminal binary decision diagrams: an efficient data structure for matrix representation”. Presented at the international workshop on logic synthesis (IWLS), Tahoe City, CA; 23–26, May, 1993.
  13. Akers SB. “Binary decision diagrams”. IEEE Trans Comput, 1978.
  14. Patel K, Markov IL, Hayes JP. “Evaluating circuit reliability under probabilistic gate-fault models”. Proceedings of the international workshop on logic synthesis (IWLS), 2003. pp. 59–64.
  15. Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP. “Accurate reliability evaluation and enhancement via probabilistic transfer matrix”, Proceedings of the design, automation and test in Europe conference, 2005.
  16. Franco DT, Vasconcelos MC, Naviner L, Naviner JF. “Reliability analysis of logic circuits based on signal probability”, 15th IEEE international conference on electronics, circuits and systems, 2008.
  17. Franco DT, Vasconcelos MC, Naviner L, Naviner JF. “Reliability of logic circuits under multiple simultaneous faults”, 51st Midwest symposium on circuits and systems, 2008.
  18. Levin VL. “Probability analysis of combination systems and their reliability”. EngCybernet1964, pp 893–901.
  19. J. TorrasFlaquer, J.M. Daveau, L. Naviner , P. Roche. “Fast reliability analysis of combinatorial logic circuits using conditional probabilities”, Microelectronics Reliability, vol. 50, no.2, pp. 1215–1218, 2010.
  20. Choudhury MR, Mohanram K. “Accurate and scalable reliability analysis of logic circuits”. Proceedings of design automation and test in Europe (DATE), 2007. pp. 1454–9.
  21. Choudhury MR, Mohanram K. “Reliability analysis of logic circuits”. IEEE Trans Comput Aided Des Integr Circuits Syst, vol. 28, no. 3, 2009.
  22. S.J. SeyyedMahdavi , K. Mohammadi. “SCRAP: Sequential circuits reliability analysis program”, Microelectronics Reliability, vol. 49, no. 3, pp. 924–933, 2009.
  23. Marquardt A, Betz V, Rose J. “Timing-driven placement for FPGAs”. FPGA 2000: 203-213
  24. Betz V, Rose J. “VPR: A new packing, placement and routing tool for FPGA research. FPL 1997: 213-222
  25. Baruch, Z., Cret, O., Giurgiu, H., "Genetic Algorithm for FPGA Placement", in Proceedings of the 12th International Conference on Control Systems and Computer Science (CSCS-12), 1999, vol. 2, pp. 121-126.
  26. Solar M, Perez J, Pulido J, Rodriguez M. “Placement and Routing of Boolean Functions in Constrained FPGAs using a Distributed Genetic Algorithm and Local Search”. Parallel and Distributed Processing Symposium, April 2006
  27. Wang K, Ning X. “Ant colony optimization for Symmetrical FPGA Placement”. Computer-Aided Design and Computer Graphics, 2009. CAD/Graphics '09. 11th IEEE International Conference on, Aug. 2009, pp. 561 - 563
  28. Wenyao X, Kijun X, Xinmin X. “A novel Placement Algorithm for Symmetrical FPGA”. ASICON 7th International Conference on, Oct. 2007, pp. 1281 – 1284.
  29. Venayagamoorhy GK, Gudise VG. “Swarm Intelligence for Digital Circuit Implementation on Field Programmable Gate Arrays Platforms”. Evolvable Hardware, Proceedings. NASA/DoD Conference on, June 2004, pp. 83 - 86
  30. Gudise VG, Venayagamoorhy GK. “FPGA Placement and Routing Using Particle Swarm Optimization”. VLSI, Proceedings. IEEE Computer society Annual Symposium on , Feb. 2004, pp. 307 - 308
  31. El-Abd M, Hassan H,Kamel MS. “Discrete and Continuous Particle Swarm Optimization for FPGA Placement”. Evolutionary Computation, IEEE Congress on , May 2009 , pp. 706 – 711.
  32. Xilinx Corporation, San Jose, CA, “Virtex 2.5 V field programmable gate arrays,” Data Sheet DS003-1, 2001.
  33. H. Asadi, M.B. Tahoori, "Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, no. 12, December 2007.
  34. XC4000 Series Field Programmable Gate Arrays ,DataSheet, www.xilinx.com.
Index Terms

Computer Science
Information Sciences

Keywords

Soft error rate SRAM_based FPGA Place and route GA ACO