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Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 18 - Number 5 |
| Year of Publication: 2011 |
| Authors: Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Devendra Giri |
10.5120/2280-2952
|
Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Devendra Giri . Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric. International Journal of Computer Applications. 18, 5 ( March 2011), 22-27. DOI=10.5120/2280-2952
Abstract
As scaling down MOSFET devices degrade device performance in term of leakage current and short channel effects. To overcome the problem a newer device Silicon-on-Insulator (SOI) MOSFET has been introduced. The Fully Depleted (FD) SOI MOSFETs also suffer from short channel effects (SCE) in the sub 65 nm regime due to reduction in threshold voltage. Several investigations are going to reduce the SCE in FD-SOI MOSFET. This work is also facilitating for the improvement of performance of FD-SOI MOSFET using high-k gate spacer dielectric. The results from sentaurus TCAD simulator show that high-k spacer dielectric increases on state driving current and reduces off leakage current due to eminent vertical fringing electric field effect. This fringing field also lessens the SCE such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS). High-k spacer dielectrics ameliorate the Ion/Ioff, transconductance and voltage gain of the FD-SOI MOSFET compare to the conventional oxide spacer.
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