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FPGA Implementation Content Addressable Memory in Cache Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 179 - Number 5 |
| Year of Publication: 2017 |
| Authors: Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta |
10.5120/ijca2017915949
|
Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta . FPGA Implementation Content Addressable Memory in Cache Applications. International Journal of Computer Applications. 179, 5 ( Dec 2017), 27-29. DOI=10.5120/ijca2017915949
Abstract
Content Addressable Memory (CAM) is a special type of high speed memory device that can support to compare all the stored data in parallel with a given input data in an efficient way and provide the address of the match data. Read, write, and match are three characteristics of a CAM memory. Read and write are operation of a CAM array in the same way as simple memory. Match mode is the unique operation of the CAM memory. CAM is frequently used in high speed searching operation such as lookup tables, communication networks, pattern recognition, data compression and real signal tracking. The match time of CAM structure is faster and employs better performance than other types of memory. Advancements in VLSI technology FPGAs have high throughput and short time to market make it most attractive in hardware industry. This paper design CAM cell in addition with dual port Synchronous Static Random Access Memory (SSRAM) in cache memory. Hardware realization of this proposed architecture is described using Hardware Description Language (HDL). The operation speed of this proposed module is 306.184MHz in Spartan-6 FPGA platform.
References
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- CAM cell is fast memory access with a cost of area. The time required to find an item stored in memory location can be drastically reduced if the item can be search by its content rather than its address. The computation speed of this CAM cell is 306.184MHz.
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