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Reseach Article

FPGA Implementation Content Addressable Memory in Cache Applications

by Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 179 - Number 5
Year of Publication: 2017
Authors: Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta
10.5120/ijca2017915949

Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta . FPGA Implementation Content Addressable Memory in Cache Applications. International Journal of Computer Applications. 179, 5 ( Dec 2017), 27-29. DOI=10.5120/ijca2017915949

@article{ 10.5120/ijca2017915949,
author = { Aditya Baidya, Sagnik Goswami, Satyam Chowdhury, Debarshi Datta },
title = { FPGA Implementation Content Addressable Memory in Cache Applications },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2017 },
volume = { 179 },
number = { 5 },
month = { Dec },
year = { 2017 },
issn = { 0975-8887 },
pages = { 27-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume179/number5/28734-2017915949/ },
doi = { 10.5120/ijca2017915949 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:54:32.643060+05:30
%A Aditya Baidya
%A Sagnik Goswami
%A Satyam Chowdhury
%A Debarshi Datta
%T FPGA Implementation Content Addressable Memory in Cache Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 179
%N 5
%P 27-29
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Content Addressable Memory (CAM) is a special type of high speed memory device that can support to compare all the stored data in parallel with a given input data in an efficient way and provide the address of the match data. Read, write, and match are three characteristics of a CAM memory. Read and write are operation of a CAM array in the same way as simple memory. Match mode is the unique operation of the CAM memory. CAM is frequently used in high speed searching operation such as lookup tables, communication networks, pattern recognition, data compression and real signal tracking. The match time of CAM structure is faster and employs better performance than other types of memory. Advancements in VLSI technology FPGAs have high throughput and short time to market make it most attractive in hardware industry. This paper design CAM cell in addition with dual port Synchronous Static Random Access Memory (SSRAM) in cache memory. Hardware realization of this proposed architecture is described using Hardware Description Language (HDL). The operation speed of this proposed module is 306.184MHz in Spartan-6 FPGA platform.

References
  1. K. Pagiamtzis and A. Sheikholeslami, “ Content Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey,” IEEE Journal of Solid-state Circuits, Vol. 41, no. 3, pp. 712-727, March 2006.
  2. Z. Ullah, M. K. Jaiswal, Y. C. Chan and R. C. C. Cheung, “FPGA Implementation of SRAM-based Ternary Content Addressable Memory,” IEEE 26th Int. Parallel and Distributed Symposium Workshops & Phd Forum, pp. 383-388, 2012.
  3. M. M. Soni, P. K. Dakhole, “FPGA Implementation of Content Addressable Memory Based Information detection System,” IEEE Xplore, 2014.
  4. L. M. Ionescu, A. G. Mazare and G. Serban, “FPGA Implementation of an Associative Content Addressable Memory,” Int. Conference on Applied Electronics, September, 2011.
  5. David E. Taylor, Edward W. Spitznagel, “On using content addressable memory for packet classification,” Applied Research Laboratory, Washington University in Saint Louis, 2005.
  6. ALTERA “Implementing High-Speed Search Applications with Altera CAM,” July, 2001.
  7. Q. Ibrahim, “Design & Implementation of High Speed Network Devices Using SRL16 Reconfigurable Content Addressable Memory (RCAM),” International Arab Journal of e-Technology, Vol. 2, No. 2, June 2011.
  8. CAM cell is fast memory access with a cost of area. The time required to find an item stored in memory location can be drastically reduced if the item can be search by its content rather than its address. The computation speed of this CAM cell is 306.184MHz.
Index Terms

Computer Science
Information Sciences

Keywords

Content addressable memory (CAM) Cache FPGA dual port SSRAM VHDL