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Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication

by Wameedh Nazar Flayyih
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 179 - Number 40
Year of Publication: 2018
Authors: Wameedh Nazar Flayyih
10.5120/ijca2018916934

Wameedh Nazar Flayyih . Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication. International Journal of Computer Applications. 179, 40 ( May 2018), 1-8. DOI=10.5120/ijca2018916934

@article{ 10.5120/ijca2018916934,
author = { Wameedh Nazar Flayyih },
title = { Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication },
journal = { International Journal of Computer Applications },
issue_date = { May 2018 },
volume = { 179 },
number = { 40 },
month = { May },
year = { 2018 },
issn = { 0975-8887 },
pages = { 1-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume179/number40/29344-2018916934/ },
doi = { 10.5120/ijca2018916934 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:57:56.722898+05:30
%A Wameedh Nazar Flayyih
%T Crosstalk Aware Multi-Bit Error Detection with Limited Error Correction Coding for Reliable On-Chip Communication
%J International Journal of Computer Applications
%@ 0975-8887
%V 179
%N 40
%P 1-8
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reliability of on-chip communication became a challenge in deep submicrometer (DSM) region due to the increased effect of the different noise sources and the crosstalk between adjacent interconnects. This led to the introduction of many coding schemes to jointly address both issues. In this paper, high error detection with single error correction joint coding scheme is proposed. The proposed scheme limits its error correction to single error as it was found that this meets the performance requirements while allowing the scheme to detect higher number of errors, namely six errors in this proposed scheme. The proposed scheme was implemented in two different designs, one optimized for higher performance and the other for smaller area. The two designs were evaluated and compared to similar coding schemes. The scheme achieved higher reliability and maintained high throughput. As compared to previous work, the first implementation achieved 4% higher frequency whereas the second implementation achieved 13% smaller area and 11% lower power.

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Index Terms

Computer Science
Information Sciences

Keywords

Error control fault tolerance network on chip

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