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Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

by Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 179 - Number 23
Year of Publication: 2018
Authors: Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami
10.5120/ijca2018916476

Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami . Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications. 179, 23 ( Feb 2018), 39-43. DOI=10.5120/ijca2018916476

@article{ 10.5120/ijca2018916476,
author = { Adel Alimoradi, Pourya Rostami Gooran, Manoocheher Karami },
title = { Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits },
journal = { International Journal of Computer Applications },
issue_date = { Feb 2018 },
volume = { 179 },
number = { 23 },
month = { Feb },
year = { 2018 },
issn = { 0975-8887 },
pages = { 39-43 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume179/number23/29011-2018916476/ },
doi = { 10.5120/ijca2018916476 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:56:16.007955+05:30
%A Adel Alimoradi
%A Pourya Rostami Gooran
%A Manoocheher Karami
%T Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 179
%N 23
%P 39-43
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a novel approach at circuit level named LSP is proposed by combination of LECTOR, Stack and Pass transistors techniques to decrease leakage power dissipation during active and standby mode. As a result, pass transistors are utilized to maintain logic state of network in the standby mode. Proposed technique simulation has been performed using HSPICE software in 32 nanometer technology with supply voltage 0.6V. According to achieved results by NAND gate and full adder circuits, sub-threshold current is decreased by 80% in compared to base case, 70% to LECTOR and 20% to Sleepy Keeper.

References
  1. N. Jayakumar, S. Paul, R. Garg, K. Gulati, and S. P. Khatri, “Minimizing and exploiting leakage in VLSI design,” Springer, 2010.
  2. P. Kumar, and R. K. Sharma, “Low voltage high performance hybrid full adder,” Engineering Science and Technology, an International Journal, Vol. 19, pp. 559–565, March, 2016.
  3. R. Taco, I. Levi, M. Lanuzza, and A. Fish, “Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD–SOI,” Science direct. Solid-State Electronics, Vol. 117, pp. 185–192, March, 2016.
  4. A. Wang, B. H. Calhoun, and A. P. Chandrakasan, “Sub–threshold design for ultra–low–power systems,” Springer. 2006.
  5. V. L. Rani, and M. M. Latha, “pass transistor–based pull–up/pull–down insertion technique for leakage power optimization in CMOS VLSI circuits,” springer, Circuits, Systems, and Signal Processing., Vol. 35, pp. 4139–4152, Nov. 2016.
  6. V. K. Sharma, M. Pattanaik, and B. Raj, “INDEP approach for leakage reduction in nanoscale CMOS circuits,” Tylor and Francis. International Journal of Electronics. Vol. 102, pp. 200–215, Jan. 2014.
  7. J. Seomun, I. Shin, and Y. Shin, “Synthesis of active–mode power gating circuits,” IEEE Tran. Vol. 31, pp. 391–403, March, 2012.
  8. M. Kavitha, and T. Govindaraj, “Low–power multimodal switch for leakage reduction and stability improvement in SRAM cell,” Arabian Journal for Science and Engineering, Vol. 41, pp. 2945–2955, Aug. 2016.
  9. P. Saini, and R. Mehra, “Leakage power reduction in CMOS VLSI circuits,” IJCA Journal, International Journal of Computer Applications., Vol. 55, pp. 42–48, 2012.
  10. S. D. Pable, and M. Hasan, “Ultra–low–power signaling challenges for subthreshold global interconnects,” Elsevier Integration, the VLSI journal, Vol. 45, pp. 186–196, March. 2012.
  11. A. Handa, J. Chawla, and G. Sharma, “A novel high performance low power CMOS NOR gate using voltage scaling and MTCMOS technique,” In IEEE Int Conf on Advances in Computing, Communications and Informatics (ICACCI), pp. 624–629, 2014.
  12. M. Seok, S. Hanson, et al, “Sleep mode analysis and optimization with minimal-sized power gating switch for ultra-low operation,” IEEE Tran on Very Large Scale Integration (VLSI) Systems., Vol. 20, pp. 605–615, April. 2012.
  13. R. Anjana, and A. K. Somkuwar, “Optimal solution of model reduction problem,” International Conference on (ICEVENT), Apr. 2013.
  14. J. N. Mistry, et al, “Active mode subclock power gating,” IEEE Tran on Very Large Scale Integration (VLSI) Systems., Vol. 22, pp. 1898–1908, Sep. 2013.
  15. V. Neema, S. S. Chouhan, and S. Tokekar, “novel circuit technique for reduction of leakage current in series/parallel PMOS/NMOS transistors Stack,” Tylor and Francis. IETE Journal of Research, Vol. 56, pp. 362–366, Sep. 2013.
  16. D. Baccarin, D. Esseni, and M. Alioto, “Mixed FBB/RBB: a novel low-leakage technique for FINFET Forced Stacks,” IEEE Tran on Very Large Scale Integration (VLSI) Systems., Vol. 20, pp. 1467–1472, Jun. 2012.
  17. T. G. Reddy, and K. Suganthi, “Super stack technique to reduce leakage power for sub 0.5-v supply voltage in VLSI circuits,” In IET International Conference on Sustainable Energy and Intelligent System., pp. 585–588, Feb. 2011.
  18. M. Sethi, et al, “A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors,” International Journal of Computer Applications., Vol. 77, pp. 30–35, 2013.
  19. A. P. Shah, V. Neema, and S. Daulatabad, “Effect of process, voltage and temperature (PVT) variations in LECTOR-B (leakage reduction technique) at 70 nm technology node,” In IEEE International Conference on Computer, Communication and Control, pp. 1–6, June. 2015.
  20. T. K. Gupta, and K. Khare, “Lector with footed-diode inverter: a technique for leakage reduction in domino circuits,” Circuits System Signal Process., Vol. 32, pp. 2707–2722, June. 2013.
  21. R. Lorenzo, and S. Chaudhury, “Review of circuit level leakage minimization techniques in CMOS VLSI circuits,” IETE Technical Review., Vol. 33, pp. 1–23, Apr. 2016.
  22. K. N. Bhargav, A. Suresh, and G. Saini, “Stacked Keeper with body bias: a new approach to reduce leakage power for low power VLSI design,” IEEE International Conference on Advanced Communication Control and Computing Teclmologies (ICACCCT), pp. 445–450, Jan. 2014.
Index Terms

Computer Science
Information Sciences

Keywords

Leakage power LECTOR technique Low power Stack technique VLSI.

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