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Hardware Implementation for Pileup Correction Algorithms in Gamma_Ray Spectroscopy

by Manar M. Ouda, Mohamed S. El_Tokhy, Sherief Hashima, Imbaby I. Mahmoud, Mohamed Amal-Eldin, Nesreen I. Ziedan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 176 - Number 6
Year of Publication: 2017
Authors: Manar M. Ouda, Mohamed S. El_Tokhy, Sherief Hashima, Imbaby I. Mahmoud, Mohamed Amal-Eldin, Nesreen I. Ziedan
10.5120/ijca2017915634

Manar M. Ouda, Mohamed S. El_Tokhy, Sherief Hashima, Imbaby I. Mahmoud, Mohamed Amal-Eldin, Nesreen I. Ziedan . Hardware Implementation for Pileup Correction Algorithms in Gamma_Ray Spectroscopy. International Journal of Computer Applications. 176, 6 ( Oct 2017), 43-48. DOI=10.5120/ijca2017915634

@article{ 10.5120/ijca2017915634,
author = { Manar M. Ouda, Mohamed S. El_Tokhy, Sherief Hashima, Imbaby I. Mahmoud, Mohamed Amal-Eldin, Nesreen I. Ziedan },
title = { Hardware Implementation for Pileup Correction Algorithms in Gamma_Ray Spectroscopy },
journal = { International Journal of Computer Applications },
issue_date = { Oct 2017 },
volume = { 176 },
number = { 6 },
month = { Oct },
year = { 2017 },
issn = { 0975-8887 },
pages = { 43-48 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume176/number6/28560-2017915634/ },
doi = { 10.5120/ijca2017915634 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:41:51.134726+05:30
%A Manar M. Ouda
%A Mohamed S. El_Tokhy
%A Sherief Hashima
%A Imbaby I. Mahmoud
%A Mohamed Amal-Eldin
%A Nesreen I. Ziedan
%T Hardware Implementation for Pileup Correction Algorithms in Gamma_Ray Spectroscopy
%J International Journal of Computer Applications
%@ 0975-8887
%V 176
%N 6
%P 43-48
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

One of the main detection duties in spectroscopy system is pileup detection of the location of the maximum peaks utilizing a local extreme method. This paper presents the hardware implementation of two pile up recovery algorithms. The first algorithm utilizes a peak detection algorithm, while the second one utilizes a peak sensitivity algorithm. The two algorithms are designed and evaluated by compiling MATLAB into field programmable gate array (FPGA) using Xilinx system generator (XSG). The tested signal is captured by analogue to-digital converter (ADC) with sampling rate of 16MS/s. The results confirm that the first algorithm is better than the second one due to its simple architecture, which leads to faster processing speed.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Pulse pile up Digital signal processing XSG FPGA

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