The week's pick
Reseach Article
Delay Reduced 4 Bit Reversible Arithmetic Logic Units
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 175 - Number 1 |
| Year of Publication: 2017 |
| Authors: Vineeta Dwivedi, Pankaj Soni, Manish Gurjar |
10.5120/ijca2017915467
|
Vineeta Dwivedi, Pankaj Soni, Manish Gurjar . Delay Reduced 4 Bit Reversible Arithmetic Logic Units. International Journal of Computer Applications. 175, 1 ( Oct 2017), 20-25. DOI=10.5120/ijca2017915467
Abstract
Power consumption is an important issue in today’s world. Growing market of electronic system replaces the conventional digital system by reversible logic circuit to solve the problem of loss of information which was dissipated in the form of heat in irreversible circuit. As digital system implemented using AND and OR gates dissipates major amount of energy in the form of bit erased during logical operation where according to R. Landuer and Bennett concludes that one bit energy loss equalize the information loss in the form of KTln2 joules per bit per cycle unavoidable heat dissipation. Thus in this project, garbage free reversible computing system investigated from abstract design to physical gate level implementation. This proposed design is compared in terms of gate count, quantum cost and propagation delay. This reversible CPU designed using Feynman gate, Peres gate, Toffoli gate and DKG gate. It is synthesized on Xilinx 6.1i ISE and simulation result verifies the correction and modification of proposed design. Survey of this paper is based on types of reversible gates and four parameter that is gate count, ancilla input, garbage output, and quantum cost. This survey had great impact on quantum computing, nanotechnology, QCA, and low power VLSI.
References
- Jayashree H V and Ashwin S, “Berger Check and Fault Tolerant Reversible Arithmetic Component Design”, Internatioanal Conference of Digital Signal Processing and Circuit System, PP. 656-659, IEEE 2015.
- Lafifa Jamal and Hafiz Md. Hasan Babu, “Design and Implementation of a Reversible Central Processing Unit”, IEEE Computer Society Annual Symposium on VLSI, Vol. 45, Issure 07, IEEE 2015.
- Hatkar A. P., Hatkar A. A. and Narkhede N. P., “ASIC Design of Reversible Multiplier Circuit”, International Conference on Electronic Systems, Signal Processing and Computing Technologies, PP. 01-07, IEEE 2014.
- Morrison and Nagarajan Ranganathan, “Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures”, Computer Society Annual Symposium on VLSI, PP. 456-461, IEEE 2013.
- Mr. Abhishek Gupta, Mr. UtsavMalviya and Prof. VinodKapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, Computer Society Annual Symposium on VLSI, PP. 01-05, IEEE 2012.
- Akanksha Dixit and Vinod Kapse, “Arithmetic & Logic Unit (ALU) Design using Reversible Control Unit”, International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 6, June 2012.
- LekshmiViswanath and Ponni.M, “Design and Analysis of 16 Bit Reversible ALU”, Volume 1, Issue 1, PP 46-53, June 2012.
- M. Morrison and N. Ranganathan, "Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures," IEEE International Symposium on VLSI, PP. 126-131, IEEE 2011.
- Md. Belayet Ali, Hosna Ara Rahman and Md. Mizanur Rahman, “Design of a High Performance Reversible Multiplier”, IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 6, No 1, November 2011.
- Indrayani Patle, Akansha Bhargav and Prashant Wanjari, “Implementation of Baugh-Wooley Multiplier Based on Soft-CoreProcessor”, IOSR Journal of Engineering (IOSRJEN), Vol. 23, Issue 05, May 2010.
- Indrayani Patle, Akansha Bhargav and Prashant Wanjari, “Implementation of Baugh-Wooley Multiplier Based on Soft-CoreProcessor”, IOSR Journal of Engineering (IOSRJEN), Vol. 23, Issue 05, May 2010
- H. Thapliyal and N. Ranganathan, "Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay, and Garbage Outputs,"ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, Issue 4, April 2010.
- H. Thapliyal and N. Ranganathan, "Reversible Logic Based Concurrently Testable Latches for Molecular QCA," IEEE Transactions on Nanotechnology, Vol. 9, Issue. 1, PP. 62-69, IEEE 2010.
- M. Nachtigal, H. Thapliyal, and N. Ranganathan, "Design of a Reversible Single Precision Floating Point Multiplier Based on Operand Decomposition," To appear in Proc. of 10th IEEE International Conference on Nanotechnology , PP. 01-06, IEEE 2010.
- M. K. Thomson, Robert Gluck and Holger Bock Axelsen, “Reversible Arithmetic Logic Unit for Quantum arithmetic”, Journal of Physics A: Mathematical and Theoretical. Volume 43, Issue 04, April 2010.
- N. Nayeem, A. Hossain, M. Haque, L. Jamal, and H. Babu, “Novel reversible division hardware,” in Circuits and Systems, MWSCAS ’09. 52nd IEEE International Midwest Symposium on, 2009, pp. 1134 –1138, IEEE 2009.
- H. Axelsen, R. Glck, and T. Yokoyama, “Reversible machine code and its abstract processor architecture,” in Computer Science Theory and Applications, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, Vol. 46, Issue 4, PP. 56–69, 2007.
- H. Thapliyal, M.B. Srinivas, “Novel design and reversible logic synthesis of multiplexer based full adder and multipliers”, 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, PP.1593-1596, August 7–10, 2005.
- M. Khan, “Design of Full-Adder with Reversible Gates,” Proceedings of 5th International Conference on Computer and Information Technology, PP. 515-519, IEEE 2002.
- D. P. DiVincenzo, “Quantum gates and circuits,” Proceedings of the Royal Society of London A: Mathematical, Physical and Engineering Sciences, vol. 454, no. 1969, pp. 261–276, 1998.
- C. H. Bennett, “Logical reversibility of computation,” IBM J. Research and Development, vol. 17, pp. 525–532, 1973.
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