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Study and Evaluate Influence of Minimizing Dimensions HEMT FET Transistor on the (I-V) Curves Characteristics
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 174 - Number 1 |
| Year of Publication: 2017 |
| Authors: Omar Ibrahim Alsaif, Kalid Kaleel Mohammed |
10.5120/ijca2017915298
|
Omar Ibrahim Alsaif, Kalid Kaleel Mohammed . Study and Evaluate Influence of Minimizing Dimensions HEMT FET Transistor on the (I-V) Curves Characteristics. International Journal of Computer Applications. 174, 1 ( Sep 2017), 10-14. DOI=10.5120/ijca2017915298
Abstract
Continuous miniaturization of HEMTs for the development of ultra high density ICs has resulted in degradation of device parameters by increasing the effects of reducing dimensions. At present time, AlGaN/GaN HEMT is considered as a backbone of both optical and microwave high power electronic applications. Gallium Nitride (GaN) is a wide band-gap semiconductor material with excellent material properties for high frequency, high power, and high temperature electronics. In this work two models of GaN field-effect transistors based on High Electron Mobility Transistors ( HEMT ) technology with different length dimensions ( 4 µm and 8 µm ) and channel length ( 0.5 µm, 1µm ) respectively. Two models have been studied and investigated using Schotcky- Read- Hall ( SRH ) model, which take in account recombination's effects and simulate currents due to voltage field and thermal leakage. Another model ( Fermi- Dirac ) are used as carrier statics model that deals about reducing carrier concentrations in the heavily doped region. Simulation results based on Silvaco Atlas TCAD software for ( I-V) diagrams of the two models, where drain voltage ( 0 to 5 V ) and four different gate source voltage applied ( 0, -1, -2, -3 V). It can be seen the drain current for ( 4 µm) model decreased to (0.346 ) when dimensions minimized ( 50 % ),when gate voltage ( -3V ), while this ratio reduced to ( 0.302 ) at gate voltage ( 0V ), and it will increased as the gate voltage increases, however drain current seems going to saturation region as the drain voltage increased, which gives the best suitability for these types of devices in the radio frequency power applications. ( Ids- Vg ) a good parameter to understand effects of reducing device dimensions, where the current ranging ( 20- 70 µA) for (4 µm) and ( 1.01 – 1.09 mA ) for the other model, at the same voltage conditions. The work has contributed to a substantial improvement in the area of device simulation and increased efficiency in device design in general, but particularly for ( GaN) HEMT nanometric technologies.
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