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SoC Memory Management for Reducing Fault Problem from Reserved Memory Components

by Abhijit Pathak
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 173 - Number 2
Year of Publication: 2017
Authors: Abhijit Pathak
10.5120/ijca2017915259

Abhijit Pathak . SoC Memory Management for Reducing Fault Problem from Reserved Memory Components. International Journal of Computer Applications. 173, 2 ( Sep 2017), 39-41. DOI=10.5120/ijca2017915259

@article{ 10.5120/ijca2017915259,
author = { Abhijit Pathak },
title = { SoC Memory Management for Reducing Fault Problem from Reserved Memory Components },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2017 },
volume = { 173 },
number = { 2 },
month = { Sep },
year = { 2017 },
issn = { 0975-8887 },
pages = { 39-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume173/number2/28310-2017915259/ },
doi = { 10.5120/ijca2017915259 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:20:12.709495+05:30
%A Abhijit Pathak
%T SoC Memory Management for Reducing Fault Problem from Reserved Memory Components
%J International Journal of Computer Applications
%@ 0975-8887
%V 173
%N 2
%P 39-41
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, the author proposes an optimal management for system on chip (SoC) memory by using the reserved memory components and solving the covering fault problem. This method will enable to realize many services, such as SoC diagnosis with given resolution of fault location, real-time functional testing of input patterns and analysis of output reactions.

References
  1. J. Bergeron, Writing Test Benches: Functional Verification of HDL Models, Springer, 2003, p. 512.
  2. Y. Zorian, Today’s SoC test challenges, in: ITC International Test Conference, 2005.
  3. S. Shoukourian, V. Vardanian, Y. Zorian, SoC Yield Optimization via an Embedded-memory Test and Repair Infrastructure, IEEE Design and Test of Computers (2004) 200-207.
  4. V. Hahanov, W. Gharibi, K. Mostovaya, Embedded method of SoC memory repairing, Electronics and Electrical Engineering 90 (2009).
  5. P. Rashinkar, P. Paterson, L. Singh, System-on-chip Verification: Methodology and Techniques, Kluwer Academic Publishers, 2002, p. 393.
  6. Y. Zorian, S. Shoukourian, Embedded-memory test and repair: infrastructure IP for SoC yield, IEEE Design and Test of Computers (2003) 58-66.
  7. Y. Zorian, A. Yessayan, IEEE 1500 utilization in SoC design and test, in: ITC International Test Conference, 2005.
  8. IEEE-1800 IEEE Standard for System Verilog Language, 2005, p. 586, available online at: http://ieeexplore.ieee. org/servlet/opac?punumber=10437.
  9. L. Youngs, S. Paramanandam, Mapping and repairing embedded-memory defects, IEEE Design and Test of Computers (1997) 18-24.
  10. A.N. Parfentiy, V.I. Hahanov, E.I. Litvinova, SOC Infrastructure intellectual property models, ASU and Automation Devices С (2007) 83-99.
  11. V.I. Hahanov, I.V. Hahanova, VHDL + Verilog = synthesis for minutes, SMIT, Kharkov, 2007, p. 264.
  12. Z. Yervant, What is infrastructure IP, IEEE Design & Test of Computers, May-June, 2002, pp. 5-7.
  13. IEEE 1500 Web Site, available online at: http://grouper. ieee.org/groups/1500/.
  14. M. F. Bondarenko, G.F. Krivoula, V.G. Ryabtsev, S.A. Fradkov, V.I. Hahanov, Design and Diagnosis of Computer Systems and Networks, NMTS VO, Кiev, 2000, p. 306.
  15. V. Hahanov, E. Litvinova, V. Obrizan, W. Gharibi, Embedded method of SoC diagnosis, Electronics and Electrical Engineering 88 (2008).
  16. V. Hahanov, W. Gharibi, K. Mostovaya, embedded method of SoC memory repairing, Electronics and Electrical Engineering 90 (2009).
Index Terms

Computer Science
Information Sciences

Keywords

Diagnosis system on chip infrastructure intellectual property fault built in repair analysis built in self repair.

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