The week's pick
Reseach Article
Temperature Sensitive Microarchitecture Design Circuit Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 173 - Number 1 |
| Year of Publication: 2017 |
| Authors: Tamanna Afroze, S. M. Farhad |
10.5120/ijca2017913824
|
Tamanna Afroze, S. M. Farhad . Temperature Sensitive Microarchitecture Design Circuit Design. International Journal of Computer Applications. 173, 1 ( Sep 2017), 1-4. DOI=10.5120/ijca2017913824
Abstract
Microprocessors are designed with very tiny microchips and heat induced due to operation makes the chip deteriorate their performance in many extents. Heat causes a portion of chip-area to get beyond tolerable temperature range which can degrade performance of many applications in chip-level. This work addresses many issues in this range. The main contribution of the work lies in reconsidering the heat transition among chips, or inside a chip in order to decrease heat inside a microprocessor. With this end in view, a renewed design architecture in circuit-level has been considered. To design the total work inside microprocessor in response to dynamic temperature change a different level of operation-mechanism has been proposed. To watch the applications running in pipeline, and then by utilizing slack time in hardware level this work wants to improve performance of the processor. In brief, total work proposes two new heat-control mechanisms, one is at operation-level and the other is at architectural-level. At operation-level, this work proposes a prediction mechanism to predict the useful operations inside the microprocessor that performs as a sink for heat dissipation. At architectural-level, this work proposes a drain system. This work has simulated the proposed system using Matlab and observed that the system works perfectly well. A comparison with existing mechanism has been devised which shows the proposed work increases performance of running application.
References
- M. Kondo and H. Nakamura. A Small, Fast and Low-Power Register File by Bit-Partitioning/Proceedings of the 11th Int’l Symposium on High-Performance Computer Architectur e,2005,pp. 1-10.
- J. Hu, K. John, and S. Wang, “Thermal-Aware Subarrayed Data Cache Microarchitectures,” International Journal of Intelligent Control and Systems, Vol.13, No. 4, December 2008, pp. 251-263.
- Y. Zhang, D. Parikh, K. Sankaranaraya nan, K. Skadron, and M. Stan, “HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects,” University of Virginia Department of Computer Science Tech. Report CS-2003-05.
- I. Park, M. D. Powell, and T. N. Vijayku mar, “Reducing Register Ports for Higher Speed and Lower Energy”, In Proceedings of MICRO, 2002.
- M.S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar, “The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays”, In the proceedings of the 29th International Symposium on Computer Architecture.
- J. Donald and M. Martonosi, “Tempera ture Aware Design Issues for SMT and CMP Architectures”, Work shop on Complexity-Effective Design, 2004.
- J. Donald and M. Martonosi, “Techn iques for Multicore Thermal Management: Classification and New E xploration”, ACM SIGARCH Computer Architecture News, 2006.
- Sheng-Chih Lin, N. Srivastava and K. Banerjee, “A Thermally –Aware Methodology for Design –Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs”, International Conference of Computer Design, 2005.
- G. H. Loh, Y. Xie, and B. Black, “Proce ssor Design in 3D Die-Stacking Technologies,” IEEE Computer Society, 2007. Pp. 31-48.
- H. Yu, Yu Hu, C. Liu, and Lei He, “Mi nimal Skew Clock Embedding Considering Time Variant Temperature G radient,” In the Proceedings of ISPLD, 2007, Austin, Texas, USA.
- Z. Qi, B. H. Meyer, W. Huang, R. J. Ri bando, K. Skadron, M. R. Stan, “Temperature-to-Power Mapping,” In the Proceedings of ICCD, 2010.
- S. Borkar, “Thousand Core Chips-A T echnology Perspective,” In the Proceedings of DAC, 2007, San Diego, California, USA.
- J. K. John, J.S. Hu , and S. G. Ziavras, “Optimizing the Thermal Behavior of Subarrayed Data Caches, ” International Conference of Computer Design, 2005.pp. 625-630.
- M. Monchiero, R. Canal, and A. Gonzalez , “Design Space Exploration for Multicore Architectures: A Power/Performance/T hermal View,” In the Proceedings of ICS, 2006, Queensland, Australia.
- K. Skadron,M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-Aware M icroarchitecture,” International Symposium on Computer Architecture, 2003.
- Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham,Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation" in MICRO 36 (2003).
- Fröhlich, B. and Plate, J. 2000. The cubic mouse: a new device for three-dimensional input. In Proceedings of the SIGCHI Conference on Human Factors in Computing Systems
- Tavel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.
- Sannella, M. J. 1994 Constraint Satisfaction and Debugging for Interactive User Interfaces. Doctoral Thesis. UMI Order Number: UMI Order No. GAX95-09398., University of Washington.
- Forman, G. 2003. An extensive empirical study of feature selection metrics for text classification. J. Mach. Learn. Res. 3 (Mar. 2003), 1289-1305.
- Brown, L. D., Hua, H., and Gao, C. 2003. A widget framework for augmented interaction in SCAPE.
- Y.T. Yu, M.F. Lau, "A comparison of MC/DC, MUMCUT and several other coverage criteria for logical decisions", Journal of Systems and Software, 2005, in press.
- Spector, A. Z. 1989. Achieving application requirements. In Distributed Systems, S. Mullender
Index Terms
Keywords