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Design and Implementation of Low Power Inexact Floating Point Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 168 - Number 7 |
| Year of Publication: 2017 |
| Authors: Kamlesh Pedraj, Jayendra Kumar |
10.5120/ijca2017914450
|
Kamlesh Pedraj, Jayendra Kumar . Design and Implementation of Low Power Inexact Floating Point Adder. International Journal of Computer Applications. 168, 7 ( Jun 2017), 43-46. DOI=10.5120/ijca2017914450
Abstract
Floating-point applications are a growing trend in the FPGA community. In nanoscale integrated circuits design as the demand for mobile computing & higher integration density is increasing power is becoming a very important constraint. Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. For some applications where error is in tolerable range an inexact circuit offers reduction in both static and dynamic power .In this paper, an inexact floating-point adder is designed by approximating exponent sub tractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. It is then observed that it greatly reduced the power consumption and hence increased the reliability.
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