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Design and Implementation of Low Power Inexact Floating Point Adder

by Kamlesh Pedraj, Jayendra Kumar
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 168 - Number 7
Year of Publication: 2017
Authors: Kamlesh Pedraj, Jayendra Kumar
10.5120/ijca2017914450

Kamlesh Pedraj, Jayendra Kumar . Design and Implementation of Low Power Inexact Floating Point Adder. International Journal of Computer Applications. 168, 7 ( Jun 2017), 43-46. DOI=10.5120/ijca2017914450

@article{ 10.5120/ijca2017914450,
author = { Kamlesh Pedraj, Jayendra Kumar },
title = { Design and Implementation of Low Power Inexact Floating Point Adder },
journal = { International Journal of Computer Applications },
issue_date = { Jun 2017 },
volume = { 168 },
number = { 7 },
month = { Jun },
year = { 2017 },
issn = { 0975-8887 },
pages = { 43-46 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume168/number7/27891-2017914450/ },
doi = { 10.5120/ijca2017914450 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:15:33.110333+05:30
%A Kamlesh Pedraj
%A Jayendra Kumar
%T Design and Implementation of Low Power Inexact Floating Point Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 168
%N 7
%P 43-46
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Floating-point applications are a growing trend in the FPGA community. In nanoscale integrated circuits design as the demand for mobile computing & higher integration density is increasing power is becoming a very important constraint. Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. For some applications where error is in tolerable range an inexact circuit offers reduction in both static and dynamic power .In this paper, an inexact floating-point adder is designed by approximating exponent sub tractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. It is then observed that it greatly reduced the power consumption and hence increased the reliability.

References
  1. Liu, Weiqiang, et al. "Design and analysis of inexact floating-point adders." IEEE Transactions on Computers 65.1 (2016): 308-314.
  2. K. Palem and A. Lingamneni, “Ten years of building broken chips: The physics and engineering of inexact computing,”ACM Trans. Embedded Comput. Syst., vol. 12, no. 2, article 87, 2013.
  3. A. Lingamneni, K. Muntimadugu, C. Enz, R. Karp, K. Palem, and C. Piguet,“Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling,” inProc. ACM Int. Conf. Comput. Frontiers, 2012,pp. 3–12.
  4. H. Mahdiani, A. Ahmadi, S. Fakhraie, and C. Lucas, “Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft computing applications,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57,no. 4, pp. 850–862, Apr. 2010.
  5. V. Gupta, D. Mohapatra, S. Park, A. Raghunathan, and K. Roy, “IMPACT: Imprecise adders for low-power approximate computing,” in Proc. Int.Symp. Low Power Electron. Des., 2011, pp. 1–3.
  6. Z. Yang, A. Jain, J. Liang, J. Han and F. Lombardi, “Approximate XORXNOR-based adders for inexact computing,” inProc. 13rd IEEE Conf. Nanotechnol., 2013, pp. 690–693.
  7. D. Mohapatra, V. Chippa, A. Raghunathan, and K. Roy, “Design of voltage scalable meta-functions for approximate computing,” inProc. Des.,Autom.Test Eur. Conf. Exhib., 2011, pp. 1–6.
  8. C. Liu, J. Han, and F. Lombardi, “An analytical framework for evaluating the error characteristics of approximate adders,” IEEE Trans. Comput.,vol. 64, no. 5, pp. 1268–1281, May 2015.
  9. C. Liu, J. Han, and F. Lombardi, “A low-power, high-performance approximate multiplier with configurable partial error recovery,” inProc. Design,Autom. Test Eur. Conf. Exhib., 2014, pp. 1–4.
  10. J. Y. Tong, D. Nagle, and R. Rutenbar, “Reducing power by optimizing then necessary precision/range of floating-point arithmetic, ”IEEE Trans. Very Large Scale Integer. Syst., vol. 8, no. 3, pp. 273–286, Jun. 2000.
  11. A. Gupta, S. Mandavalli, V. Mooney, K. Ling, A. Basu, H. Johan, and B.Tandianus, “Low power probabilistic floating-point multiplier design,” in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2011, pp. 182–187.
  12. F. Fang, T. Chen, and R. Rutenbar, “Floating-point bit-width optimizationfor low-power signal processing applications,” in Proc. IEEE Int. Conf.Acoust., Speech, Signal Process., 2002, vol. 3, pp. 3208–3211.
  13. W. Liu, L, Chen, C. Wang, M. O’Neill, and F. Lombardi, “Inexact floatingpoint adder for dynamic image processing,” in Proc. 14th IEEE Conf. Nanotechnol., 2014, pp. 239–243.
  14. IEEE Standard for Floating-Point Arithmetic, IEEE Std 754-2008, Aug. 29,2008.
  15. J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate and probabilistic adders,” IEEE Trans.Comput., vol. 62, no. 9, pp. 1760–1771, Sep. 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Floating-point adders low power high dynamic range image inexact circuits error analysis.

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