International Journal of Computer Applications |
Foundation of Computer Science (FCS), NY, USA |
Volume 168 - Number 6 |
Year of Publication: 2017 |
Authors: Anuradha Savadi, Raju Yanamshetti, Jyoti Godihal |
![]() |
Anuradha Savadi, Raju Yanamshetti, Jyoti Godihal . Design and Synthesis of High Performance Vedic DSP Processor. International Journal of Computer Applications. 168, 6 ( Jun 2017), 27-32. DOI=10.5120/ijca2017914469
To satisfy the prerequisite of rapid speed signal processing design of high performance DSP processor is renowned. This paper represents a novel design and FPGA based pursuit of 64 bit DSP processor. The proposed design implicates multistage pipeline architecture and vedic algorithms to improve the speed. The DSP processor is rich with multiple application specific instructions (ASIP). The verilog HDL is used and the validated through extensive simulation. Synthesis results and attainment scrutiny of each systems components confirmed significant performance meliorism in the proffered DSP processor over the extant one..