The week's pick
Reseach Article
Design of Booth Multiplier using Double Gate MOSFET
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 167 - Number 4 |
| Year of Publication: 2017 |
| Authors: Yogeesh K.V., Venkateshkumar H. |
10.5120/ijca2017914241
|
Yogeesh K.V., Venkateshkumar H. . Design of Booth Multiplier using Double Gate MOSFET. International Journal of Computer Applications. 167, 4 ( Jun 2017), 19-23. DOI=10.5120/ijca2017914241
Abstract
Double gate MOSFET technology is used wherever low power delay product is desired. It uses to reduce leakage current drain induced barrier lowering effect (DIBL) and other short channel affects. In this work 8×8, Booth Multiplier is analysed in 90nm technology, with one single-gate MOSFET technology and then other using the proposed that is Double-Gate MOSFET technique. Depending on the input patterns, the proposed technique saves 24% in power consumption has observed in proposed circuit. Design and simulations are performed in cadence virtuoso and spectre tools using 90nm technology.
References
- J.S. Kim, H.M. Oh; C. W. Byeon; J. H. Son; J. H. Lee; J. Lee; C. Y. Kim, “V-band×8 Frequency Multiplier with optimized structure and high Spectral Purity Using 65-nm CMOS Process” in IEE Microwave and Wireless Components Letters, Vol.PP, no99,pp..1-3.
- M. Zamin Ali Khan1, Hussain Saleem2, Shiraz Afzal3 and Jawed Naseem4, “An Efficient 16-Bit Multiplier based on Booth Algorithm”, International Journal of Advancements In Research and Technology, Volume1, Issue 6, November-2012 ISSN-2278-7763
- M. Singh, A. K. Maurya, S. P. Singh and S. K. Balasubramanin, “6×6 Booth Multiplier Implemented in Modified Split-path data driven dynamic 4 logic," Students Conference on Engineering and Systems, Allahabad, 2014, pp.1-4.
- J. K. Sahani and S. Singh, “Design of Full Adder Circuit Using Double Gate MOSFET”, 2015 Fifth international Conference on Advanced Computing and Communication Technologies, Harayana 2015 pp.-57-60.
- J. L. Beuchat and J. M. Muller “Multiplication algorithms for radix-2 RN-codings and Two’s Complement numbers” 2005 IEEE International Conference On Application-Specific Systems, Architecture Processors (ASAP’05), 2005, pp.-303-308.
- S. –R. Kuang, J. P. Wang, and C.-Y. Guo, “Modified Booth multipliers with a regular partial product array,” IEE Trans. Circuit Syst. II, Exp. Briefs, vol. 56, no. 5, pp.404-408, May 2009.
- M. Vesterbacka, “A New six-transistor CMOS XOR Circuits with complementary output,” Proc. 42nd Midwest Symp. On Circuits and Systems, Las Cruces, NM, Aug. 1999.
Index Terms
Keywords